APIC code for ben

094e3bfd · Silas Boyd-Wickizer · 0cfbec15 · 094e3bfd · 094e3bfd
--- a/include/bits.hh
+++ b/include/bits.hh
@@ -85,3 +85,8 @@

 // CPUID function 0x00000005
 #define CPUID_MWAIT         0x00000005
+
+// APIC Base Address Register MSR
+#define MSR_APIC_BAR        0x0000001b
+#define APIC_BAR_XAPIC_EN   (1 << 11)
+#define APIC_BAR_X2APIC_EN  (1 << 10)
--- a/kernel/lapic.cc
+++ b/kernel/lapic.cc
@@ -78,6 +78,23 @@ void
 initlapic(void)
 {
  u64 count;
+  u64 apicbar;
+
+  // See Intel Arch. Manual Vol 3a, the APIC section
+  // Check if x2APIC is enabled, disable it if so..
+  apicbar = readmsr(MSR_APIC_BAR);
+  if (apicbar & APIC_BAR_X2APIC_EN) {
+    // Disable x2APIC and the xAPIC
+    apicbar &= ~(APIC_BAR_XAPIC_EN | APIC_BAR_X2APIC_EN);
+    writemsr(MSR_APIC_BAR, apicbar);
+    // Re-enable the xAPIC
+    apicbar |= APIC_BAR_XAPIC_EN;
+    writemsr(MSR_APIC_BAR, apicbar);
+    // Sanity-check..
+    u32 ebx;
+    cpuid(CPUID_FEATURES, 0, &ebx, 0, 0);
+    assert(lapic[ID]>>24 == FEATURE_EBX_APIC(ebx));
+  }

  // Enable local APIC; set spurious interrupt vector.
  lapicw(SVR, ENABLE | (T_IRQ0 + IRQ_SPURIOUS));
@@ -146,10 +163,19 @@ lapicid(void)
      __builtin_return_address(0));
  }

+  // To be safe, read the APIC ID from the CPUID register
+  u32 ebx;
+  cpuid(CPUID_FEATURES, 0, &ebx, 0, 0);
+  return HWID(FEATURE_EBX_APIC(ebx));
+
+#if 0
+  // It should be safe to read from the APIC's MMIO anytime,
+  // but it's not.  The BIOS might have enabled the x2APIC,
+  // in which case the value of lapic[ID]>>24 is undefined.
  if (lapic == nullptr)
    panic("lapicid");
-
  return HWID(lapic[ID]>>24);
+#endif
 }

 // Acknowledge interrupt.