oops - wrong bit (vic zandy)

eadbd55a · rsc · c2258bf4 · eadbd55a
--- a/ioapic.c
+++ b/ioapic.c
@@ -17,7 +17,7 @@
 // The first (low) register in a pair contains configuration bits.
 // The second (high) register contains a bitmask telling which
 // CPUs can serve that interrupt.
-#define INT_DISABLED   0x00100000  // Interrupt disabled
+#define INT_DISABLED   0x00010000  // Interrupt disabled
 #define INT_LEVEL      0x00008000  // Level-triggered (vs edge-)
 #define INT_ACTIVELOW  0x00002000  // Active low (vs high)
 #define INT_LOGICAL    0x00000800  // Destination is CPU id (vs APIC ID)