Skip to content

H
Hardware-IRQ
提交 f4bf5fe7 创建 作者: 李川's avatar 李川 提交者： 李川
浏览文件
操作

修改硬中断实验项目

上级 66800a49
全部展开 隐藏空白字符变更
内嵌 并排
正在显示 包含 0 行增加 和 1078 行删除
ALU.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir1 NETU1_1 NETFLAG_^EN NETALU0_S0 NETALU0_S1 NETALU0_S2 NETW_^EN NETA_^EN NETA_CLK DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 NETFLAG_Q3 NETFLAG_Q0 NETL_GATE_^EN NETR_GATE_^EN NETD_GATE_^EN NETALU0_S3 NETALU0_CN NETALU0_M DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 NETA_CLK
xALU0 NETALU0_^A0 NETALU0_^A1 NETALU0_^A2 NETALU0_^A3 NETALU0_^B0 NETALU0_^B1 NETALU0_^B2 NETALU0_^B3 NETALU0_S0 NETALU0_S1 NETALU0_S2 NETALU0_S3 NETALU0_CN NETALU0_M NETALU0_^G NETALU0_^P NETALU0_AEQB NETALU0_CN4 NETALU0_^F3 NETALU0_^F2 NETALU0_^F1 NETALU0_^F0 74LS181
xALU1 NETALU1_^A0 NETALU1_^A1 NETALU1_^A2 NETALU1_^A3 NETALU1_^B0 NETALU1_^B1 NETALU1_^B2 NETALU1_^B3 NETALU0_S0 NETALU0_S1 NETALU0_S2 NETALU0_S3 NETALU0_CN4 NETALU0_M NETALU1_^G NETALU1_^P NETALU1_AEQB NETALU1_CN4 NETALU1_^F3 NETALU1_^F2 NETALU1_^F1 NETALU1_^F0 74LS181
.subckt 74LS181 ^A0 ^A1 ^A2 ^A3 ^B0 ^B1 ^B2 ^B3 S0 S1 S2 S3 CN M ^G ^P AEQB CN4 ^F3 ^F2 ^F1 ^F0
aU1 [ ^B3 S3 ^A3] NetU1_4 AND3
aU2 [ ^A3 S2 NetU2_3] NetU2_4 AND3
aU9 [ NetU10_1 NetU10_2 NetU28_2] NetU14_3 AND3
aU19 [ ^B2 S3 ^A2] NetU19_4 AND3
aU20 [ ^A2 S2 NetU20_3] NetU20_4 AND3
aU28 [ NetU10_2 NetU28_2 NetU26_5] NetU28_4 AND3
aU33 [ ^B1 S3 ^A1] NetU33_4 AND3
aU34 [ ^A1 S2 NetU34_3] NetU34_4 AND3
aU41 [ NetU10_3 NetU10_4 NetU26_5] NetU41_4 AND3
aU46 [ ^B0 S3 ^A0] NetU46_4 AND3
aU47 [ ^A0 S2 NetU47_3] NetU47_4 AND3
aU54 [ CN NetU11_4 NetU26_5] NetU54_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU1_4 NetU2_4] NetU10_1 NOR
aU23 [ NetU19_4 NetU20_4] NetU10_2 NOR
aU37 [ NetU33_4 NetU34_4] NetU10_3 NOR
aU52 [ NetU46_4 NetU47_4] NetU11_4 NOR
aU57 [ NetU54_4 NetU55_3] NetU45_2 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU2_3 S1] NetU4_3 AND
aU5 [ S0 ^B3] NetU5_3 AND
aU6 [ NetU10_1 NetU24_4] NetU14_2 AND
aU21 [ NetU20_3 S1] NetU21_3 AND
aU22 [ S0 ^B2] NetU22_3 AND
aU29 [ NetU24_4 NetU26_5] NetU29_3 AND
aU35 [ NetU34_3 S1] NetU35_3 AND
aU36 [ S0 ^B1] NetU36_3 AND
aU42 [ NetU28_2 NetU26_5] NetU42_3 AND
aU48 [ NetU47_3 S1] NetU48_3 AND
aU49 [ S0 ^B0] NetU49_3 AND
aU55 [ NetU10_4 NetU26_5] NetU55_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU4_3 NetU5_3 ^A3] NetU13_2 NOR3
aU24 [ NetU21_3 NetU22_3 ^A2] NetU24_4 NOR3
aU38 [ NetU35_3 NetU36_3 ^A1] NetU28_2 NOR3
aU44 [ NetU40_5 NetU41_4 NetU42_3] NetU31_2 NOR3
aU51 [ NetU48_3 NetU49_3 ^A0] NetU10_4 NOR3
.model NOR3 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU8 ^B3 NetU2_3 NOT
aU15 ^G NetU15_2 NOT
aU17 NetU11_6 NetU16_2 NOT
aU25 ^B2 NetU20_3 NOT
aU39 ^B1 NetU34_3 NOT
aU50 ^B0 NetU47_3 NOT
aU56 M NetU26_5 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] NetU10_5 AND4
aU27 [ NetU10_3 NetU10_2 NetU10_4 NetU26_5] NetU27_5 AND4
aU40 [ CN NetU11_4 NetU10_3 NetU26_5] NetU40_5 AND4
aU60 [ ^F3 ^F2 ^F1 ^F0] AEQB AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU11 [ NetU10_1 NetU10_2 NetU10_3 NetU11_4 CN] NetU11_6 NAND5
.model NAND5 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU12 [ NetU10_1 NetU10_2 NetU10_3 NetU11_4] ^P NAND4
.model NAND4 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU13 [ NetU10_1 NetU13_2] NetU13_3 XOR
aU18 [ NetU13_3 NetU18_2] ^F3 XOR
aU30 [ NetU10_2 NetU24_4] NetU30_3 XOR
aU31 [ NetU30_3 NetU31_2] ^F2 XOR
aU43 [ NetU10_3 NetU28_2] NetU43_3 XOR
aU45 [ NetU43_3 NetU45_2] ^F1 XOR
aU53 [ NetU11_4 NetU10_4] NetU53_3 XOR
aU59 [ NetU53_3 NetU58_3] ^F0 XOR
.model XOR d_xor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU14 [ NetU13_2 NetU14_2 NetU14_3 NetU10_5] ^G NOR4
aU32 [ NetU26_6 NetU27_5 NetU28_4 NetU29_3] NetU18_2 NOR4
.model NOR4 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU16 [ NetU15_2 NetU16_2] CN4 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU26 [ CN NetU11_4 NetU10_3 NetU10_2 NetU26_5] NetU26_6 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU58 [ CN NetU26_5] NetU58_3 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU1 [ NETU1_1 NETFLAG_Q3] NETL_GATE_A0 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU23 NETL_GATE_^EN NETU23_2 NOT
aU24 NETR_GATE_^EN NETU24_2 NOT
aU6 NETALU1_CN4 NETU29_3 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU29 [ NETU26_4 NETU27_4 NETU29_3] NETFLAG_D3 OR3
.model OR3 d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 [ NETALU0_^F3 NETALU0_^F2 NETALU0_^F1 NETALU0_^F0] NETU2_5 OR4
aU4 [ NETALU1_^F3 NETALU1_^F2 NETALU1_^F1 NETALU1_^F0] NETU3_1 OR4
.model OR4 d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU26 [ NETU23_2 NETU1_1 NETALU1_^F3] NETU26_4 AND3
aU27 [ NETU24_2 NETU1_1 NETALU0_^F0] NETU27_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NETU3_1 NETU2_5] NETFLAG_D0 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xL_gate NETL_GATE_A0 NETALU0_^F0 NETALU0_^F1 NETALU0_^F2 NETALU0_^F3 NETALU1_^F0 NETALU1_^F1 NETALU1_^F2 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETL_GATE_^EN BUS_TRANS8
xD_gate NETALU0_^F0 NETALU0_^F1 NETALU0_^F2 NETALU0_^F3 NETALU1_^F0 NETALU1_^F1 NETALU1_^F2 NETALU1_^F3 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETD_GATE_^EN BUS_TRANS8
xR_gate NETALU0_^F1 NETALU0_^F2 NETALU0_^F3 NETALU1_^F0 NETALU1_^F1 NETALU1_^F2 NETALU1_^F3 NETL_GATE_A0 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETR_GATE_^EN BUS_TRANS8
.subckt BUS_TRANS8 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 EN
xU3 EN IEN NNOT
xU5 A0 IA0 NNOT
xU6 A1 IA1 NNOT
xU7 A2 IA2 NNOT
xU8 A3 IA3 NNOT
xU9 A4 IA4 NNOT
xU10 A5 IA5 NNOT
xU11 A6 IA6 NNOT
xU12 A7 IA7 NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
a1 [ IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7] IEN [ B0 B1 B2 B3 B4 B5 B6 B7] MULTI_TRISTATE
.model MULTI_TRISTATE d_multristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)
.ends
xA DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETALU0_^A0 NETALU0_^A1 NETALU0_^A2 NETALU0_^A3 NETALU1_^A0 NETALU1_^A1 NETALU1_^A2 NETALU1_^A3 NETA_^EN NETA_CLK REG_EN8
xW DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETALU0_^B0 NETALU0_^B1 NETALU0_^B2 NETALU0_^B3 NETALU1_^B0 NETALU1_^B1 NETALU1_^B2 NETALU1_^B3 NETW_^EN NETA_CLK REG_EN8
xFLAG NETFLAG_D0 NETFLAG_D1 NETFLAG_D2 NETFLAG_D3 NETFLAG_D4 NETFLAG_D5 NETFLAG_D6 NETFLAG_D7 NETFLAG_Q0 NETFLAG_Q1 NETFLAG_Q2 NETFLAG_Q3 NETFLAG_Q4 NETFLAG_Q5 NETFLAG_Q6 NETFLAG_Q7 NETFLAG_^EN NETA_CLK REG_EN8
.subckt REG_EN8 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ENABLE CLOCK
aU1 [ Q7 NetU1_2] NetU1_3 AND
aU3 [ 8D NetU14_2] NetU3_3 AND
aU7 [ Q6 NetU7_2] NetU10_1 AND
aU8 [ 7D NetU14_2] NetU10_2 AND
aU13 [ Q5 NetU13_2] NetU13_3 AND
aU14 [ 6D NetU14_2] NetU14_3 AND
aU19 [ Q4 NetU19_2] NetU19_3 AND
aU20 [ 5D NetU14_2] NetU20_3 AND
aU25 [ Q3 NetU25_2] NetU25_3 AND
aU26 [ 4D NetU14_2] NetU26_3 AND
aU31 [ Q2 NetU31_2] NetU31_3 AND
aU32 [ 3D NetU14_2] NetU32_3 AND
aU37 [ Q1 NetU37_2] NetU37_3 AND
aU38 [ 2D NetU14_2] NetU38_3 AND
aU39 [ Q0 NetU39_2] NetU39_3 AND
aU40 [ 1D NetU14_2] NetU40_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 NetU14_2 NetU1_2 NOT
aU6 NetU4_3 NetU5_D NOT
aU9 NetU14_2 NetU7_2 NOT
aU11 NetU10_3 NetU11_2 NOT
aU15 NetU14_2 NetU13_2 NOT
aU17 NetU16_3 NetU17_2 NOT
aU22 NetU14_2 NetU19_2 NOT
aU23 NetU21_3 NetU23_2 NOT
aU28 NetU14_2 NetU25_2 NOT
aU29 NetU27_3 NetU29_2 NOT
aU33 NetU14_2 NetU31_2 NOT
aU35 NetU34_3 NetU35_2 NOT
aU41 NetU14_2 NetU37_2 NOT
aU44 NetU42_3 NetU44_2 NOT
aU45 NetU43_3 NetU45_2 NOT
aU48 NetU14_2 NetU39_2 NOT
aU50 EN NetU14_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU1_3 NetU3_3] NetU4_3 NOR
aU10 [ NetU10_1 NetU10_2] NetU10_3 NOR
aU16 [ NetU13_3 NetU14_3] NetU16_3 NOR
aU21 [ NetU19_3 NetU20_3] NetU21_3 NOR
aU27 [ NetU25_3 NetU26_3] NetU27_3 NOR
aU34 [ NetU31_3 NetU32_3] NetU34_3 NOR
aU42 [ NetU37_3 NetU38_3] NetU42_3 NOR
aU43 [ NetU39_3 NetU40_3] NetU43_3 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 NetU5_D CLK NetU12_^CLR NetU12_^CLR Q7 NetU5_^Q 74LS74D
aU12 NetU11_2 CLK NetU12_^CLR NetU12_^CLR Q6 NetU12_^Q 74LS74D
aU18 NetU17_2 CLK NetU12_^CLR NetU12_^CLR Q5 NetU18_^Q 74LS74D
aU24 NetU23_2 CLK NetU12_^CLR NetU12_^CLR Q4 NetU24_^Q 74LS74D
aU30 NetU29_2 CLK NetU12_^CLR NetU12_^CLR Q3 NetU30_^Q 74LS74D
aU36 NetU35_2 CLK NetU12_^CLR NetU12_^CLR Q2 NetU36_^Q 74LS74D
aU46 NetU44_2 CLK NetU12_^CLR NetU12_^CLR Q1 NetU46_^Q 74LS74D
aU47 NetU45_2 CLK NetU12_^CLR NetU12_^CLR Q0 NetU47_^Q 74LS74D
.model 74LS74D d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
xU49 NetU12_^CLR CONSTANT0
.subckt CONSTANT0 constant0
VV1 Net1_1 0 DC 0
a1 [Net1_1] [constant0] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
xUClk CLOCK CLK NNOT
xUEN ENABLE EN NNOT
xU2 Q0 1Q NNOT
xU3 Q1 2Q NNOT
xU4 Q3 4Q NNOT
xU5 Q2 3Q NNOT
xU6 Q4 5Q NNOT
xU7 Q5 6Q NNOT
xU8 Q6 7Q NNOT
xU9 Q7 8Q NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
.ends
.ends
CU.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
差异被折叠。
DM1000.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
Circuit Title
.tran 1ms 50s
xC2 NETC2_1 SCLK
xCLOCK NETCLOCK_1 SCLK
xRESET RESET SCLK
xC3 NETC3_1 SCLK
xC4 NETC4_1 SCLK
xC5 NETC5_1 SCLK
xC6 NETC6_1 SCLK
xC7 NETC7_1 SCLK
xC8 NETC8_1 SCLK
xC9 NETC9_1 SCLK
xC10 NETC10_1 SCLK
.subckt SCLK out
v1 1 0 DC 5
v2 3 0 DC 0
r1 1 2 1k
abridge1 [2] [out] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s1 2 0 3 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends
xRIN NET1_1 NET1_2 NET1_3 NET1_4 NET1_5 NET1_6 NET1_7 NET1_8 NETRIN_GATE_A0 NETRIN_GATE_A1 NETRIN_GATE_A2 NETRIN_GATE_A3 NETRIN_GATE_A4 NETRIN_GATE_A5 NETRIN_GATE_A6 NETRIN_GATE_A7 NETRIN_^EN NETC2_1 REG_EN8
xROUT DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETROUT_Q0 NETROUT_Q1 NETROUT_Q2 NETROUT_Q3 NETROUT_Q4 NETROUT_Q5 NETROUT_Q6 NETROUT_Q7 ROUT_REG_EN CLK REG_EN8
xMAR DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETMAR_GATE_A0 NETMAR_GATE_A1 NETMAR_GATE_A2 NETMAR_GATE_A3 NETMAR_GATE_A4 NETMAR_GATE_A5 NETMAR_GATE_A6 NETMAR_GATE_A7 MAR_REG_EN CLK REG_EN8
.subckt REG_EN8 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ENABLE CLOCK
aU1 [ Q7 NetU1_2] NetU1_3 AND
aU3 [ 8D NetU14_2] NetU3_3 AND
aU7 [ Q6 NetU7_2] NetU10_1 AND
aU8 [ 7D NetU14_2] NetU10_2 AND
aU13 [ Q5 NetU13_2] NetU13_3 AND
aU14 [ 6D NetU14_2] NetU14_3 AND
aU19 [ Q4 NetU19_2] NetU19_3 AND
aU20 [ 5D NetU14_2] NetU20_3 AND
aU25 [ Q3 NetU25_2] NetU25_3 AND
aU26 [ 4D NetU14_2] NetU26_3 AND
aU31 [ Q2 NetU31_2] NetU31_3 AND
aU32 [ 3D NetU14_2] NetU32_3 AND
aU37 [ Q1 NetU37_2] NetU37_3 AND
aU38 [ 2D NetU14_2] NetU38_3 AND
aU39 [ Q0 NetU39_2] NetU39_3 AND
aU40 [ 1D NetU14_2] NetU40_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 NetU14_2 NetU1_2 NOT
aU6 NetU4_3 NetU5_D NOT
aU9 NetU14_2 NetU7_2 NOT
aU11 NetU10_3 NetU11_2 NOT
aU15 NetU14_2 NetU13_2 NOT
aU17 NetU16_3 NetU17_2 NOT
aU22 NetU14_2 NetU19_2 NOT
aU23 NetU21_3 NetU23_2 NOT
aU28 NetU14_2 NetU25_2 NOT
aU29 NetU27_3 NetU29_2 NOT
aU33 NetU14_2 NetU31_2 NOT
aU35 NetU34_3 NetU35_2 NOT
aU41 NetU14_2 NetU37_2 NOT
aU44 NetU42_3 NetU44_2 NOT
aU45 NetU43_3 NetU45_2 NOT
aU48 NetU14_2 NetU39_2 NOT
aU50 EN NetU14_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU1_3 NetU3_3] NetU4_3 NOR
aU10 [ NetU10_1 NetU10_2] NetU10_3 NOR
aU16 [ NetU13_3 NetU14_3] NetU16_3 NOR
aU21 [ NetU19_3 NetU20_3] NetU21_3 NOR
aU27 [ NetU25_3 NetU26_3] NetU27_3 NOR
aU34 [ NetU31_3 NetU32_3] NetU34_3 NOR
aU42 [ NetU37_3 NetU38_3] NetU42_3 NOR
aU43 [ NetU39_3 NetU40_3] NetU43_3 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 NetU5_D CLK NetU12_^CLR NetU12_^CLR Q7 NetU5_^Q 74LS74D
aU12 NetU11_2 CLK NetU12_^CLR NetU12_^CLR Q6 NetU12_^Q 74LS74D
aU18 NetU17_2 CLK NetU12_^CLR NetU12_^CLR Q5 NetU18_^Q 74LS74D
aU24 NetU23_2 CLK NetU12_^CLR NetU12_^CLR Q4 NetU24_^Q 74LS74D
aU30 NetU29_2 CLK NetU12_^CLR NetU12_^CLR Q3 NetU30_^Q 74LS74D
aU36 NetU35_2 CLK NetU12_^CLR NetU12_^CLR Q2 NetU36_^Q 74LS74D
aU46 NetU44_2 CLK NetU12_^CLR NetU12_^CLR Q1 NetU46_^Q 74LS74D
aU47 NetU45_2 CLK NetU12_^CLR NetU12_^CLR Q0 NetU47_^Q 74LS74D
.model 74LS74D d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
xU49 NetU12_^CLR CONSTANT0
.subckt CONSTANT0 constant0
VV1 Net1_1 0 DC 0
a1 [Net1_1] [constant0] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
xUClk CLOCK CLK NNOT
xUEN ENABLE EN NNOT
xU2 Q0 1Q NNOT
xU3 Q1 2Q NNOT
xU4 Q3 4Q NNOT
xU5 Q2 3Q NNOT
xU6 Q4 5Q NNOT
xU7 Q5 6Q NNOT
xU8 Q6 7Q NNOT
xU9 Q7 8Q NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
.ends
x1 NET1_1 NET1_2 NET1_3 NET1_4 NET1_5 NET1_6 NET1_7 NET1_8 INTER_DIGITAL8
.subckt INTER_DIGITAL8 D0 D1 D2 D3 D4 D5 D6 D7
x1 D0 DCT
x2 D1 DCT
x3 D2 DCT
x4 D3 DCT
x5 D4 DCT
x6 D5 DCT
x7 D6 DCT
x8 D7 DCT
.subckt DCT out
v1 1 0 DC 5
v2 3 0 DC 2
r1 1 2 1k
abridge1 [2] [out] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s1 2 0 3 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends
.ends
xRIN_gate NETRIN_GATE_A0 NETRIN_GATE_A1 NETRIN_GATE_A2 NETRIN_GATE_A3 NETRIN_GATE_A4 NETRIN_GATE_A5 NETRIN_GATE_A6 NETRIN_GATE_A7 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 RIN_GATE_EN BUS_TRANS8
xMAR_gate NETMAR_GATE_A0 NETMAR_GATE_A1 NETMAR_GATE_A2 NETMAR_GATE_A3 NETMAR_GATE_A4 NETMAR_GATE_A5 NETMAR_GATE_A6 NETMAR_GATE_A7 ABUS0 ABUS1 ABUS2 ABUS3 ABUS4 ABUS5 ABUS6 ABUS7 MAR_GATE_EN BUS_TRANS8
.subckt BUS_TRANS8 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 EN
xU3 EN IEN NNOT
xU5 A0 IA0 NNOT
xU6 A1 IA1 NNOT
xU7 A2 IA2 NNOT
xU8 A3 IA3 NNOT
xU9 A4 IA4 NNOT
xU10 A5 IA5 NNOT
xU11 A6 IA6 NNOT
xU12 A7 IA7 NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
a1 [ IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7] IEN [ B0 B1 B2 B3 B4 B5 B6 B7] MULTI_TRISTATE
.model MULTI_TRISTATE d_multristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)
.ends
xU1 NETCLOCK_1 CLK NETU1_2 LTri_Gate
xU2 NETC1_1 CLK NET6_1 LTri_Gate
.subckt LTri_Gate 1 2 3
aU1 1 NetU1_2 2 BUFFER
.model BUFFER d_tristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)
aU2 3 NetU1_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
x6 NET6_1 INTER_DIGITAL
x7 IF INTER_DIGITAL
.subckt INTER_DIGITAL out
v1 1 0 DC 5
v2 3 0 DC 2
r1 1 2 1k
abridge1 [2] [out] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s1 2 0 3 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends
aU3 NET6_1 NETU1_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xC1 NETC1_1 CLOCK1
.subckt CLOCK1 out frequency = 100 dutycycle = 0.5 risedelay = 1e-6 falldelay = 1e-6
v1 1 0 DC 2
a1 1 out var_clock
.model var_clock d_osc(cntl_array = [-1.0 0.0 1.0 2.0] freq_array = [10 100 1e3 {frequency}] duty_cycle ={dutycycle} init_phase = 0 rise_delay = {risedelay} fall_delay = {falldelay})
.ends
x2 NET2_1 P
.subckt P 1
a1 1 2 InputBuffer
a2 2 Digload
.MODEL Digload d_pulldown(load = 1e-12)
.MODEL InputBuffer d_buffer (rise_delay = 1n fall_delay = 1n)
.ends
xALU CN FLAG_REG_EN S0 S1 S2 W_REG_EN A_REG_EN CLK DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 CF ZF L_GATE_EN R_GATE_EN D_GATE_EN S3 C M DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 CLK modulecir1
xREG IR0 IR1 REG_WR REG_READ CLK IA_GATE_EN SP_GATE_EN ASR_GATE_EN IA_REG_EN SP_REG_EN ASR_REG_EN CST_U\D CST_LOAD CST_GATE_EN DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 modulecir2
xPC CF ZF IR2 IR3 PC_LOAD_EN CLK DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 PC_A_GATE_EN PC_D_GATE_EN PC_ADD INTR_LOAD DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 ABUS7 ABUS6 ABUS5 ABUS4 ABUS3 ABUS2 ABUS1 ABUS0 RESET modulecir3
xMEM ABUS7 ABUS6 ABUS5 ABUS4 ABUS3 ABUS2 ABUS1 ABUS0 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 MEM_WR CLK MEM_GATE_EN DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 modulecir4
xCU CLK DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 IR0 IR1 IR2 IR3 S0 S1 S2 A_REG_EN W_REG_EN FLAG_REG_EN CN REG_WR SP_REG_EN ROUT_REG_EN MAR_GATE_EN MAR_REG_EN PC_LOAD_EN PC_A_GATE_EN ASR_REG_EN MEM_WR IA_REG_EN SP_GATE_EN PC_D_GATE_EN D_GATE_EN R_GATE_EN L_GATE_EN ASR_GATE_EN IA_GATE_EN RIN_GATE_EN MEM_GATE_EN CST_GATE_EN CST_LOAD REG_READ S3 C M CST_U\D PC_ADD INTR INTR_LOAD IF RESET INTA2 EOI INTA1 modulecir5
xIRQ NETC3_1 NETC4_1 NETC5_1 NETC6_1 NETC7_1 NETC8_1 NETC9_1 NETC10_1 INTA2 EOI RESET NET2_1 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 INTA1 RESET CLK INTA2 modulecir7
.include "D:\codecode\Hardware-IRQ\ALU.dlsche.cir"
.include "D:\codecode\Hardware-IRQ\REG.dlsche.cir"
.include "D:\codecode\Hardware-IRQ\PC.dlsche.cir"
.include "D:\codecode\Hardware-IRQ\MEM.dlsche.cir"
.include "D:\codecode\Hardware-IRQ\CU.dlsche.cir"
.include "D:\codecode\Hardware-IRQ\IRQ.dlsche.cir"
.end
DM1000.dlsche.svg deleted 100644 → 0
浏览文件 @ 66800a49
这个 源代码变更 因为 太大 而不能显示。 你可以 浏览blob 。
H-IRQ.dlsche.svg deleted 100644 → 0
浏览文件 @ 66800a49
这个 源代码变更 因为 太大 而不能显示。 你可以 浏览blob 。
HDINT.dlsche.svg deleted 100644 → 0
浏览文件 @ 66800a49
差异被折叠。
IRR.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir8 NETU17_A NETU17_B NETU17_C NETU10_1 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 IRR0 IRR1 IRR2 IRR3 IRR4 IRR5 IRR6 IRR7 NETU11_2 NETU20_2
aU10 NETU10_1 NETU10_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xU17 NETU17_G1 NETU17_^G2A NETU17_^G2B NETU17_A NETU17_B NETU17_C NETU11_1 NETU12_1 NETU13_1 NETU14_1 NETU15_1 NETU16_1 NETU17_Y6 NETU17_Y7 74LS138D
.subckt 74LS138D G1 ^G2A ^G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
aU1 [ G1 NetU1_2 NetU1_3] NetU10_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 ^G2A NetU1_2 NOT
aU3 ^G2B NetU1_3 NOT
aU4 A NetU10_1 NOT
aU5 B NetU10_2 NOT
aU6 C NetU11_3 NOT
aU15 NetU10_1 NetU11_1 NOT
aU16 NetU10_2 NetU11_2 NOT
aU17 NetU11_3 NetU10_3 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU10_4 NetU11_2 NetU11_1 NetU10_3] Y7 NAND4
aU8 [ NetU10_1 NetU10_3 NetU11_2 NetU10_4] Y6 NAND4
aU9 [ NetU10_2 NetU10_3 NetU11_1 NetU10_4] Y5 NAND4
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] Y4 NAND4
aU11 [ NetU11_1 NetU11_2 NetU11_3 NetU10_4] Y3 NAND4
aU12 [ NetU10_1 NetU11_2 NetU11_3 NetU10_4] Y2 NAND4
aU13 [ NetU11_1 NetU10_2 NetU11_3 NetU10_4] Y1 NAND4
aU14 [ NetU10_1 NetU10_2 NetU11_3 NetU10_4] Y0 NAND4
.model NAND4 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU1 NETU1_D IR0 NETU1_PR NETU11_3 IRR0 NETU1_^Q D_FLOP
aU2 NETU1_D IR1 NETU2_PR NETU12_3 IRR1 NETU2_^Q D_FLOP
aU3 NETU1_D IR2 NETU3_PR NETU13_3 IRR2 NETU3_^Q D_FLOP
aU4 NETU1_D IR3 NETU4_PR NETU14_3 IRR3 NETU4_^Q D_FLOP
aU5 NETU1_D IR4 NETU5_PR NETU15_3 IRR4 NETU5_^Q D_FLOP
aU6 NETU1_D IR5 NETU6_PR NETU16_3 IRR5 NETU6_^Q D_FLOP
aU7 NETU1_D IR6 NETU7_PR NETU18_3 IRR6 NETU7_^Q D_FLOP
aU8 NETU1_D IR7 NETU8_PR NETU19_3 IRR7 NETU8_^Q D_FLOP
.model D_FLOP d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
xU9 NETU1_D DIGITAL1
.subckt DIGITAL1 constant1
VV1 Net1_1 0 DC 3.5
a1 [Net1_1] [constant1] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
xU11 NETU11_1 NETU11_2 NETU11_3 NNOR
xU12 NETU12_1 NETU11_2 NETU12_3 NNOR
xU13 NETU13_1 NETU11_2 NETU13_3 NNOR
xU14 NETU14_1 NETU11_2 NETU14_3 NNOR
xU15 NETU15_1 NETU11_2 NETU15_3 NNOR
xU16 NETU16_1 NETU11_2 NETU16_3 NNOR
xU18 NETU17_Y6 NETU11_2 NETU18_3 NNOR
xU19 NETU17_Y7 NETU11_2 NETU19_3 NNOR
.subckt NNOR 1 2 3
aU1 1 NetU1_2 NOT
aU2 2 NetU2_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU1_2 NetU2_2] 3 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU20 [ NETU10_2 NETU20_2] NETU17_G1 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
ISR.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir9 NETU11_1 NETU12_1 NETU18_1Q NETU18_2Q NETU18_3Q NETU2_G1 NET9_CLR ISR7 ISR6 ISR5 ISR4 ISR3 ISR2 ISR1 ISR0 IRNM0 IRNM1 IRNM2 NETU11_2 NETU11_2
xU2 NETU2_G1 NETU2_^G2A NETU2_^G2B IRNM0 IRNM1 IRNM2 NET1_^EN NET2_^EN NET3_^EN NET4_^EN NET5_^EN NET6_^EN NET7_^EN NET8_^EN 74LS138D
xU15 NETU15_G1 NETU15_^G2A NETU15_^G2B NETU15_A NETU15_B NETU15_C NET9_D0 NET9_D1 NET9_D2 NET9_D3 NET9_D4 NET9_D5 NET9_D6 NET9_D7 74LS138D
.subckt 74LS138D G1 ^G2A ^G2B A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
aU1 [ G1 NetU1_2 NetU1_3] NetU10_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 ^G2A NetU1_2 NOT
aU3 ^G2B NetU1_3 NOT
aU4 A NetU10_1 NOT
aU5 B NetU10_2 NOT
aU6 C NetU11_3 NOT
aU15 NetU10_1 NetU11_1 NOT
aU16 NetU10_2 NetU11_2 NOT
aU17 NetU11_3 NetU10_3 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU10_4 NetU11_2 NetU11_1 NetU10_3] Y7 NAND4
aU8 [ NetU10_1 NetU10_3 NetU11_2 NetU10_4] Y6 NAND4
aU9 [ NetU10_2 NetU10_3 NetU11_1 NetU10_4] Y5 NAND4
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] Y4 NAND4
aU11 [ NetU11_1 NetU11_2 NetU11_3 NetU10_4] Y3 NAND4
aU12 [ NetU10_1 NetU11_2 NetU11_3 NetU10_4] Y2 NAND4
aU13 [ NetU11_1 NetU10_2 NetU11_3 NetU10_4] Y1 NAND4
aU14 [ NetU10_1 NetU10_2 NetU11_3 NetU10_4] Y0 NAND4
.model NAND4 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU4 ISR7 NETU3_D0 NOT
aU5 ISR6 NETU3_D1 NOT
aU6 ISR5 NETU3_D2 NOT
aU7 ISR4 NETU3_D3 NOT
aU8 ISR3 NETU3_D4 NOT
aU9 ISR2 NETU3_D5 NOT
aU10 ISR1 NETU10_2 NOT
aU14 ISR0 NETU14_2 NOT
aU37 NETU37_1 NETU15_G1 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
x1 NET1_D NET1_CLK NET1_PR NET1_CLR NET1_^EN ISR0 NET1_^Q DCP_FLOP
x2 NET1_D NET1_CLK NET2_PR NET2_CLR NET2_^EN ISR1 NET2_^Q DCP_FLOP
x3 NET1_D NET1_CLK NET3_PR NET3_CLR NET3_^EN ISR2 NET3_^Q DCP_FLOP
x4 NET1_D NET1_CLK NET4_PR NET4_CLR NET4_^EN ISR3 NET4_^Q DCP_FLOP
x5 NET1_D NET1_CLK NET5_PR NET5_CLR NET5_^EN ISR4 NET5_^Q DCP_FLOP
x6 NET1_D NET1_CLK NET6_PR NET6_CLR NET6_^EN ISR5 NET6_^Q DCP_FLOP
x7 NET1_D NET1_CLK NET7_PR NET7_CLR NET7_^EN ISR6 NET7_^Q DCP_FLOP
x8 NET1_D NET1_CLK NET8_PR NET8_CLR NET8_^EN ISR7 NET8_^Q DCP_FLOP
.subckt DCP_FLOP D CLK PR CLR EN Q NQ
aU1 EN NETU1_2 NOT
aU2 NETU1_2 NETU2_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NETU1_2 D] NETU3_3 AND
aU4 [ Q NETU2_2] NETU4_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 [ NETU4_3 NETU3_3] NETU5_3 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU6 NETU5_3 CLK PR CLR Q NQ D_FLOP
.model D_FLOP d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
.ends
xU1 NET1_D CONSTANT1
xU30 NETU18_^CLR CONSTANT1
.subckt CONSTANT1 constant1
VV1 Net1_1 0 DC 3.5
a1 [Net1_1] [constant1] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
xU3 NETU3_D0 NETU3_D1 NETU3_D2 NETU3_D3 NETU3_D4 NETU3_D5 NETU10_2 NETU14_2 NETU3_^EI NETU3_EO NETU37_1 NETU15_C NETU15_B NETU15_A 74LS148D
.subckt 74LS148D D0 D1 D2 D3 D4 D5 D6 D7 EI EO GS A2 A1 A0
aU1 D2 NetU10_1 NOT
aU2 NetU10_1 NetU2_2 NOT
aU18 D1 NetU18_2 NOT
aU19 D3 NetU11_1 NOT
aU20 D4 NetU14_1 NOT
aU21 D5 NetU15_1 NOT
aU22 D6 NetU12_1 NOT
aU23 EI NetU10_4 NOT
aU24 D7 NetU13_1 NOT
aU25 NetU14_1 NetU10_2 NOT
aU26 NetU15_1 NetU10_3 NOT
aU27 NetU12_1 NetU27_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU18_2 NetU2_2 NetU10_2 NetU27_2 NetU10_4] NetU29_1 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU11_1 NetU10_2 NetU27_2 NetU10_4] NetU29_2 AND4
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] NetU10_5 AND4
aU11 [ NetU11_1 NetU10_2 NetU10_3 NetU10_4] NetU11_5 AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 [ D6 D7 NetU10_4] NetU5_4 NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU6 [ D0 D1 D2 D3 D4 D5] NetU6_7 NAND6
.model NAND6 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU9 [ NetU13_1 NetU10_4] NetU29_4 AND
aU12 [ NetU12_1 NetU10_4] NetU12_3 AND
aU13 [ NetU13_1 NetU10_4] NetU13_3 AND
aU14 [ NetU14_1 NetU10_4] NetU14_3 AND
aU15 [ NetU15_1 NetU10_4] NetU15_3 AND
aU16 [ NetU12_1 NetU10_4] NetU16_3 AND
aU17 [ NetU13_1 NetU10_4] NetU17_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU8 [ NetU15_1 NetU27_2 NetU10_4] NetU29_3 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU6_7 NetU5_4] EO OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU28 [ EO NetU10_4] GS NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU29 [ NetU29_1 NetU29_2 NetU29_3 NetU29_4] A0 NOR4
aU30 [ NetU10_5 NetU11_5 NetU12_3 NetU13_3] A1 NOR4
aU31 [ NetU14_3 NetU15_3 NetU16_3 NetU17_3] A2 NOR4
.model NOR4 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU11 [ NETU11_1 NETU11_2] NET1_CLK OR
aU12 [ NETU12_1 NETU11_2] NET9_CLK OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xU18 IRNM0 IRNM1 IRNM2 NETU18_4D NETU18_^CLR NET1_CLK NETU18_^4Q NETU18_4Q NETU18_^3Q NETU18_3Q NETU18_^2Q NETU18_2Q NETU18_^1Q NETU18_1Q 74LS175D
.subckt 74LS175D 1D 2D 3D 4D ^CLR CLK ^4Q 4Q ^3Q 3Q ^2Q 2Q ^1Q 1Q
aU1 4D CLK NetU1_^PR NetU1_^CLR 4Q ^4Q 74LS74D
aU2 3D CLK NetU1_^PR NetU1_^CLR 3Q ^3Q 74LS74D
aU3 2D CLK NetU1_^PR NetU1_^CLR 2Q ^2Q 74LS74D
aU4 1D CLK NetU1_^PR NetU1_^CLR 1Q ^1Q 74LS74D
.model 74LS74D d_dff(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
aU5 ^CLR NetU1_^CLR NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xU6 NetU1_^PR CONSTANT0
.subckt CONSTANT0 constant0
VV1 Net1_1 0 DC 0
a1 [Net1_1] [constant0] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
.ends
x9 NET9_D0 NET9_D1 NET9_D2 NET9_D3 NET9_D4 NET9_D5 NET9_D6 NET9_D7 NET9_Q0 NET9_Q1 NET9_Q2 NET9_Q3 NET9_Q4 NET9_Q5 NET9_Q6 NET9_Q7 NET9_CLR NET9_PR NET9_EN NET9_CLK REG_AA8
.subckt REG_AA8 D0 D1 D2 D3 D4 D5 D6 D7 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLR PR ENABLE CLOCK
xU1 CLOCK CLK NNOT
xU3 ENABLE EN NNOT
xU4 PR SET NNOT
xU5 Q0 1Q NNOT
xU6 Q1 2Q NNOT
xU7 Q2 3Q NNOT
xU8 Q3 4Q NNOT
xU9 Q4 5Q NNOT
xU10 Q5 6Q NNOT
xU11 Q6 7Q NNOT
xU12 Q7 8Q NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
aU2 CLR CLEAR NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
a1 [ D0 D1 D2 D3 D4 D5 D6 D7 ] CLK SET CLEAR EN [ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 ] REG
.model REG d_registor(clk_delay = 13.0e-9 set_delay = 25.0e-9 reset_delay = 27.0e-9 en_delay = 27.0e-9ic = 2 rise_delay = 10.0e-9 fall_delay = 3e-9)
.ends
xU13 NET9_Q0 NET9_CLR NET1_CLR NNOR
xU16 NET9_Q1 NET9_CLR NET2_CLR NNOR
xU17 NET9_Q2 NET9_CLR NET3_CLR NNOR
xU19 NET9_Q3 NET9_CLR NET4_CLR NNOR
xU20 NET9_Q4 NET9_CLR NET5_CLR NNOR
xU21 NET9_Q5 NET9_CLR NET6_CLR NNOR
xU22 NET9_Q6 NET9_CLR NET7_CLR NNOR
xU23 NET9_Q7 NET9_CLR NET8_CLR NNOR
.subckt NNOR 1 2 3
aU1 1 NetU1_2 NOT
aU2 2 NetU2_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU1_2 NetU2_2] 3 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
.ends
MEM.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir4 ABUS7 ABUS6 ABUS5 ABUS4 ABUS3 ABUS2 ABUS1 ABUS0 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 NETRAM_^W\R NETRAM_CLK NETMEM_GATE_^EN DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0
xMEM_gate NETMEM_GATE_A0 NETMEM_GATE_A1 NETMEM_GATE_A2 NETMEM_GATE_A3 NETMEM_GATE_A4 NETMEM_GATE_A5 NETMEM_GATE_A6 NETMEM_GATE_A7 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETMEM_GATE_^EN BUS_TRANS8
.subckt BUS_TRANS8 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 EN
xU3 EN IEN NNOT
xU5 A0 IA0 NNOT
xU6 A1 IA1 NNOT
xU7 A2 IA2 NNOT
xU8 A3 IA3 NNOT
xU9 A4 IA4 NNOT
xU10 A5 IA5 NNOT
xU11 A6 IA6 NNOT
xU12 A7 IA7 NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
a1 [ IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7] IEN [ B0 B1 B2 B3 B4 B5 B6 B7] MULTI_TRISTATE
.model MULTI_TRISTATE d_multristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)
.ends
xRAM ABUS0 ABUS1 ABUS2 ABUS3 ABUS4 ABUS5 ABUS6 ABUS7 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETMEM_GATE_A0 NETMEM_GATE_A1 NETMEM_GATE_A2 NETMEM_GATE_A3 NETMEM_GATE_A4 NETMEM_GATE_A5 NETMEM_GATE_A6 NETMEM_GATE_A7 NETRAM_^W\R NETRAM_CLK 256RAM1
.subckt 256RAM1 A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 WE CLK
xU1 A0 ADDRESS0 NNOT
xU2 A1 ADDRESS1 NNOT
xU3 A2 ADDRESS2 NNOT
xU4 A3 ADDRESS3 NNOT
xU5 A4 ADDRESS4 NNOT
xU6 A5 ADDRESS5 NNOT
xU7 A6 ADDRESS6 NNOT
xU8 A7 ADDRESS7 NNOT
xU9 D0 DATAIN0 NNOT
xU10 D1 DATAIN1 NNOT
xU11 D2 DATAIN2 NNOT
xU12 D3 DATAIN3 NNOT
xU13 D4 DATAIN4 NNOT
xU14 D5 DATAIN5 NNOT
xU15 D6 DATAIN6 NNOT
xU16 D7 DATAIN7 NNOT
xU17 WE WRITEENABLE NNOT
xU18 CLK CLOCK NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
vcc 1 0 DC 5
v0 C0 0 DC 2
v1 C1 0 DC 2
v2 C2 0 DC 2
v3 C3 0 DC 2
v4 C4 0 DC 2
v5 C5 0 DC 2
v6 C6 0 DC 2
v7 C7 0 DC 2
r0 1 r0_2 1k
r1 1 r1_2 1k
r2 1 r2_2 1k
r3 1 r3_2 1k
r4 1 r4_2 1k
r5 1 r5_2 1k
r6 1 r6_2 1k
r7 1 r7_2 1k
abridge0 [r0_2] [Q0] adc_buff
abridge1 [r1_2] [Q1] adc_buff
abridge2 [r2_2] [Q2] adc_buff
abridge3 [r3_2] [Q3] adc_buff
abridge4 [r4_2] [Q4] adc_buff
abridge5 [r5_2] [Q5] adc_buff
abridge6 [r6_2] [Q6] adc_buff
abridge7 [r7_2] [Q7] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 1)
s0 r0_2 0 c0 0 switch ON
s1 r1_2 0 c1 0 switch ON
s2 r2_2 0 c2 0 switch ON
s3 r3_2 0 c3 0 switch ON
s4 r4_2 0 c4 0 switch ON
s5 r5_2 0 c5 0 switch ON
s6 r6_2 0 c6 0 switch ON
s7 r7_2 0 c7 0 switch ON
.model switch sw vt=1 vh=0.2 ron=1 roff=1k
.ends
.ends
PC.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir3 NETU1_D0 NETU1_D1 NETU1_A NETU1_B NETU1_C NETPC_CLK DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 NETPC_GATE_^EN NETPC_D_GATE_^EN NETPC_EN NETU3_1 DBUS7 DBUS6 DBUS5 DBUS4 DBUS3 DBUS2 DBUS1 DBUS0 ABUS7 ABUS6 ABUS5 ABUS4 ABUS3 ABUS2 ABUS1 ABUS0 NETPC_^CLR
xU1 NETU1_A NETU1_B NETU1_C NETU1_^G NETU1_D0 NETU1_D1 NETU1_D2 NETU1_D2 NETU1_D4 NETU1_D5 NETU1_D6 NETU1_D7 NETU1_Y NETU1_W 74LS151D
.subckt 74LS151D A B C G D0 D1 D2 D3 D4 D5 D6 D7 Y W
aU1 [ NetU15_2 B NetU13_2 D2 NetU16_2] NetU1_6 AND5
aU2 [ B A NetU15_2 D3 NetU16_2] NetU2_6 AND5
aU3 [ C NetU14_2 NetU13_2 D4 NetU16_2] NetU10_1 AND5
aU4 [ C A NetU14_2 D5 NetU16_2] NetU10_2 AND5
aU5 [ C B NetU13_2 D6 NetU16_2] NetU10_3 AND5
aU6 [ C B A D7 NetU16_2] NetU10_4 AND5
aU7 [ NetU15_2 NetU14_2 A D1 NetU16_2] NetU7_6 AND5
aU8 [ NetU15_2 NetU14_2 NetU13_2 D0 NetU16_2] NetU8_6 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU9 [ NetU8_6 NetU7_6 NetU1_6 NetU2_6] NetU11_1 OR4
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] NetU10_5 OR4
.model OR4 d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU11 [ NetU11_1 NetU10_5] Y OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU12 Y W NOT
aU13 A NetU13_2 NOT
aU14 B NetU14_2 NOT
aU15 C NetU15_2 NOT
aU16 G NetU16_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
xU2 NETU1_D2 CONSTANT1
.subckt CONSTANT1 constant1
VV1 Net1_1 0 DC 3.5
a1 [Net1_1] [constant1] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
aU3 [ NETU3_1 NETU1_W] NETPC_^LOAD AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xPC DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETPC_D_GATE_A0 NETPC_D_GATE_A1 NETPC_D_GATE_A2 NETPC_D_GATE_A3 NETPC_D_GATE_A4 NETPC_D_GATE_A5 NETPC_D_GATE_A6 NETPC_D_GATE_A7 NETPC_EN NETPC_^LOAD NETPC_^CLR NETPC_RCO NETPC_CLK C_SAB8
.subckt C_SAB8 D0 D1 D2 D3 D4 D5 D6 D7 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q ENABLE LOAD CLR RCO CLOCK
xU1 D0 D1 D2 D3 EN EN LOAD CLR CLK NETU1_RC0 Q3 Q2 Q1 Q0 74LS161D
xU2 D4 D5 D6 D7 NETU1_RC0 NETU1_RC0 LOAD CLR CLK CO Q7 Q6 Q5 Q4 74LS161D
.subckt 74LS161D A B C D ENP ENT ^LOAD ^CLR CLK RC0 QD QC QB QA
aU1 ^LOAD NetU1_2 NOT
aU2 ^CLR NetU2_2 NOT
aU20 ^CLR NetU11_^CLR NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU6 [ NetU12_2 NetU10_2] NetU6_3 NAND
aU13 [ NetU12_2 NetU13_2] NetU13_3 NAND
aU22 [ NetU12_2 NetU22_2] NetU22_3 NAND
aU28 [ NetU12_2 NetU28_2] NetU28_3 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU1_2 NetU2_2] NetU12_2 OR
aU8 [ NetU26_4 NetU12_2] NetU10_1 OR
aU12 [ NetU12_1 NetU12_2] NetU12_3 OR
aU21 [ NetU21_1 NetU12_2] NetU21_3 OR
aU27 [ NetU26_5 NetU12_2] NetU27_3 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ QA NetU26_4] NetU12_1 AND
aU9 [ NetU6_3 NetU10_1] NetU11_J AND
aU10 [ NetU10_1 NetU10_2] NetU10_3 AND
aU15 [ NetU13_3 NetU12_3] NetU15_3 AND
aU16 [ NetU12_3 NetU13_2] NetU16_3 AND
aU24 [ NetU22_3 NetU21_3] NetU19_J AND
aU25 [ NetU21_3 NetU22_2] NetU19_K AND
aU30 [ NetU28_3 NetU27_3] NetU18_J AND
aU31 [ NetU27_3 NetU28_2] NetU18_K AND
aU33 [ ENP ENT] NetU26_4 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 [ QB QA NetU26_4] NetU21_1 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ A ^CLR NetU12_2] NetU10_2 NAND3
aU14 [ B ^CLR NetU12_2] NetU13_2 NAND3
aU23 [ C ^CLR NetU12_2] NetU22_2 NAND3
aU29 [ D NetU12_2 ^CLR] NetU28_2 NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU26 [ QC QB QA NetU26_4] NetU26_5 AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU32 [ QD QC QB QA ENT] RC0 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU11 NetU11_J NetU10_3 CLK NetU11_^PR NetU11_^CLR QA NetU11_^Q 74LS76N_1
aU17 NetU15_3 NetU16_3 CLK NetU11_^PR NetU11_^CLR QB NetU17_^Q 74LS76N_1
aU19 NetU19_J NetU19_K CLK NetU11_^PR NetU11_^CLR QC NetU19_^Q 74LS76N_1
aU18 NetU18_J NetU18_K CLK NetU11_^PR NetU11_^CLR QD NetU18_^Q 74LS76N_1
.model 74LS76N_1 d_jkff(clk_delay = 1.0e-9 set_delay = 1e-9 reset_delay = 1e-9 ic = 0 rise_delay = 1.0e-9 fall_delay = 1e-9)
xU34 NetU11_^PR CONSTANT0_1
.subckt CONSTANT0_1 constant0
VV1 Net1_1 0 DC 0
a1 [Net1_1] [constant0] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
.ends
xUClk CLOCK CLK NNOT
xUEN ENABLE EN NNOT
xU3 Q0 1Q NNOT
xU4 Q1 2Q NNOT
xU5 Q2 3Q NNOT
xU6 Q3 4Q NNOT
xU7 Q4 5Q NNOT
xU8 Q5 6Q NNOT
xU9 Q6 7Q NNOT
xU10 Q7 8Q NNOT
xU11 CO RCO NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
.ends
xPC_gate NETPC_D_GATE_A0 NETPC_D_GATE_A1 NETPC_D_GATE_A2 NETPC_D_GATE_A3 NETPC_D_GATE_A4 NETPC_D_GATE_A5 NETPC_D_GATE_A6 NETPC_D_GATE_A7 ABUS0 ABUS1 ABUS2 ABUS3 ABUS4 ABUS5 ABUS6 ABUS7 NETPC_GATE_^EN BUS_TRANS8
xPC_D_gate NETPC_D_GATE_A0 NETPC_D_GATE_A1 NETPC_D_GATE_A2 NETPC_D_GATE_A3 NETPC_D_GATE_A4 NETPC_D_GATE_A5 NETPC_D_GATE_A6 NETPC_D_GATE_A7 DBUS0 DBUS1 DBUS2 DBUS3 DBUS4 DBUS5 DBUS6 DBUS7 NETPC_D_GATE_^EN BUS_TRANS8
.subckt BUS_TRANS8 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 EN
xU3 EN IEN NNOT
xU5 A0 IA0 NNOT
xU6 A1 IA1 NNOT
xU7 A2 IA2 NNOT
xU8 A3 IA3 NNOT
xU9 A4 IA4 NNOT
xU10 A5 IA5 NNOT
xU11 A6 IA6 NNOT
xU12 A7 IA7 NNOT
.subckt NNOT IN OUT
aU1 IN NetU1_2 NOT
aU2 NetU1_2 OUT NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
a1 [ IA0 IA1 IA2 IA3 IA4 IA5 IA6 IA7] IEN [ B0 B1 B2 B3 B4 B5 B6 B7] MULTI_TRISTATE
.model MULTI_TRISTATE d_multristate(delay = 0.5e-9 input_load = 0.5e-12 enable_load = 0.5e-12)
.ends
.ends
PR.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir10 ISR7 ISR6 ISR5 ISR4 ISR3 ISR2 ISR1 ISR0 IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0 NETU2_3 NETU15_A0 NETU15_A1 NETU15_A2
aU11 ISR7 NETU11_2 NOT
aU12 ISR6 NETU12_2 NOT
aU13 ISR5 NETU13_2 NOT
aU14 ISR4 NETU14_2 NOT
aU16 ISR3 NETU16_2 NOT
aU17 ISR2 NETU17_2 NOT
aU18 ISR1 NETU18_2 NOT
aU19 ISR0 NETU19_2 NOT
aU21 IRR7 NETU15_D0 NOT
aU22 IRR6 NETU15_D1 NOT
aU23 IRR5 NETU15_D2 NOT
aU24 IRR4 NETU15_D3 NOT
aU25 IRR3 NETU15_D4 NOT
aU26 IRR2 NETU15_D5 NOT
aU27 IRR1 NETU15_D6 NOT
aU28 IRR0 NETU15_D7 NOT
aU4 NETU15_GS NETU2_2 NOT
aU5 NETU5_1 NETU1_AGTB NOT
aU8 NETU1_OALTB NETU20_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 [ NETU20_3 NETU2_2] NETU2_3 AND
aU20 [ NETU1_OAGTB NETU20_2] NETU20_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
xU15 NETU15_D0 NETU15_D1 NETU15_D2 NETU15_D3 NETU15_D4 NETU15_D5 NETU15_D6 NETU15_D7 NETU15_^EI NETU15_EO NETU15_GS NETU15_A2 NETU15_A1 NETU15_A0 74LS148D
xU7 NETU11_2 NETU12_2 NETU13_2 NETU14_2 NETU16_2 NETU17_2 NETU18_2 NETU19_2 NETU7_^EI NETU5_1 NETU7_GS NETU1_A2 NETU1_A1 NETU1_A0 74LS148D
.subckt 74LS148D D0 D1 D2 D3 D4 D5 D6 D7 EI EO GS A2 A1 A0
aU1 D2 NetU10_1 NOT
aU2 NetU10_1 NetU2_2 NOT
aU18 D1 NetU18_2 NOT
aU19 D3 NetU11_1 NOT
aU20 D4 NetU14_1 NOT
aU21 D5 NetU15_1 NOT
aU22 D6 NetU12_1 NOT
aU23 EI NetU10_4 NOT
aU24 D7 NetU13_1 NOT
aU25 NetU14_1 NetU10_2 NOT
aU26 NetU15_1 NetU10_3 NOT
aU27 NetU12_1 NetU27_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU18_2 NetU2_2 NetU10_2 NetU27_2 NetU10_4] NetU29_1 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU11_1 NetU10_2 NetU27_2 NetU10_4] NetU29_2 AND4
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] NetU10_5 AND4
aU11 [ NetU11_1 NetU10_2 NetU10_3 NetU10_4] NetU11_5 AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU5 [ D6 D7 NetU10_4] NetU5_4 NAND3
.model NAND3 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU6 [ D0 D1 D2 D3 D4 D5] NetU6_7 NAND6
.model NAND6 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU9 [ NetU13_1 NetU10_4] NetU29_4 AND
aU12 [ NetU12_1 NetU10_4] NetU12_3 AND
aU13 [ NetU13_1 NetU10_4] NetU13_3 AND
aU14 [ NetU14_1 NetU10_4] NetU14_3 AND
aU15 [ NetU15_1 NetU10_4] NetU15_3 AND
aU16 [ NetU12_1 NetU10_4] NetU16_3 AND
aU17 [ NetU13_1 NetU10_4] NetU17_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU8 [ NetU15_1 NetU27_2 NetU10_4] NetU29_3 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU6_7 NetU5_4] EO OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU28 [ EO NetU10_4] GS NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU29 [ NetU29_1 NetU29_2 NetU29_3 NetU29_4] A0 NOR4
aU30 [ NetU10_5 NetU11_5 NetU12_3 NetU13_3] A1 NOR4
aU31 [ NetU14_3 NetU15_3 NetU16_3 NetU17_3] A2 NOR4
.model NOR4 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
xU1 NETU1_A3 NETU1_B3 NETU1_A2 NETU15_A2 NETU1_A1 NETU15_A1 NETU1_A0 NETU15_A0 NETU1_AGTB NETU1_AEQB NETU1_ALTB NETU1_OALTB NETU1_OAEQB NETU1_OAGTB 74LS85D
.subckt 74LS85D A3 B3 A2 B2 A1 B1 A0 B0 AGTB AEQB ALTB OALTB OAEQB OAGTB
aU1 [ A3 B3] NetU1_3 NAND
aU11 [ A2 B2] NetU11_3 NAND
aU24 [ A1 B1] NetU19_2 NAND
aU28 [ A0 B0] NetU21_4 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU2 [ A3 NetU1_3] NetU2_3 AND
aU3 [ NetU1_3 B3] Net17_1 AND
aU5 [ B3 NetU1_3] NetU37_1 AND
aU13 [ A2 NetU11_3] NetU12_1 AND
aU14 [ NetU11_3 B2] NetU12_2 AND
aU19 [ A1 NetU19_2] NetU18_1 AND
aU20 [ NetU19_2 B1] NetU18_2 AND
aU26 [ A0 NetU21_4] NetU25_1 AND
aU27 [ NetU21_4 B0] NetU25_2 AND
aU29 [ NetU1_3 A3] NetU29_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU2_3 Net17_1] NetU10_1 NOR
aU12 [ NetU12_1 NetU12_2] NetU10_2 NOR
aU18 [ NetU18_1 NetU18_2] NetU10_3 NOR
aU25 [ NetU25_1 NetU25_2] NetU10_4 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU6 [ B2 NetU11_3 NetU10_1] NetU38_1 AND3
aU23 [ NetU10_1 NetU11_3 A2] NetU23_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ B1 NetU19_2 NetU10_1 NetU10_2] NetU39_1 AND4
aU22 [ NetU10_2 NetU10_1 NetU19_2 A1] NetU22_5 AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU8 [ B0 NetU21_4 NetU10_1 NetU10_2 NetU10_3] NetU40_1 AND5
aU9 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4 ALTB] NetU41_1 AND5
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4 AEQB] NetU10_6 AND5
aU15 [ NetU10_1 NetU10_2 AEQB NetU10_3 NetU10_4] OAEQB AND5
aU16 [ AEQB NetU10_4 NetU10_3 NetU10_2 NetU10_1] NetU16_6 AND5
aU17 [ AGTB NetU10_4 NetU10_2 NetU10_3 NetU10_1] NetU17_6 AND5
aU21 [ NetU10_3 NetU10_2 NetU10_1 NetU21_4 A0] NetU21_6 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU30 NetU29_3 NetU30_2 NOT
aU31 NetU23_4 NetU31_2 NOT
aU32 NetU22_5 NetU32_2 NOT
aU33 NetU21_6 NetU33_2 NOT
aU34 NetU17_6 NetU34_2 NOT
aU35 NetU16_6 NetU35_2 NOT
aU37 NetU37_1 NetU37_2 NOT
aU38 NetU38_1 NetU38_2 NOT
aU39 NetU39_1 NetU39_2 NOT
aU40 NetU40_1 NetU40_2 NOT
aU41 NetU41_1 NetU41_2 NOT
aU42 NetU10_6 NetU42_2 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU36 [ NetU35_2 NetU34_2 NetU33_2 NetU32_2 NetU31_2 NetU30_2] OALTB AND6
aU43 [ NetU37_2 NetU38_2 NetU39_2 NetU40_2 NetU41_2 NetU42_2] OAGTB AND6
.model AND6 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
x17 Net17_1 PROB
.subckt PROB 1
a1 1 2 InputBuffer
a2 2 Digload
.MODEL Digload d_pulldown(load = 1e-12)
.MODEL InputBuffer d_buffer (rise_delay = 1n fall_delay = 1n)
.ends
.ends
.ends
REG.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
差异被折叠。
uPC_NEXT.dlsche.cir deleted 100644 → 0
浏览文件 @ 66800a49
.subckt modulecir6 UPC15 UPC14 UPC13 UPC12 UPC11 UPC10 UPC9 UPC8 UPC7 UPC6 UPC5 UPC4 UPC3 UPC2 UPC1 UPC0 UPC_NEXT15 UPC_NEXT14 UPC_NEXT13 UPC_NEXT12 UPC_NEXT11 UPC_NEXT10 UPC_NEXT9 UPC_NEXT8 UPC_NEXT7 UPC_NEXT6 UPC_NEXT5 UPC_NEXT4 UPC_NEXT3 UPC_NEXT2 UPC_NEXT1 UPC_NEXT0
xU1 UPC0 UPC1 UPC2 UPC3 B0 B1 B2 B3 NETU1_CN NETU1_S1 NETU1_S2 NETU1_CN NETU1_CN NETU1_M NETU1_^G NETU1_^P NETU1_AEQB NETU1_CN4 UPC_NEXT3 UPC_NEXT2 UPC_NEXT1 UPC_NEXT0 74LS181
xU2 UPC4 UPC5 UPC6 UPC7 B4 B5 B6 B7 NETU1_CN NETU2_S1 NETU2_S2 NETU1_CN NETU1_CN4 NETU2_M NETU2_^G NETU2_^P NETU2_AEQB NETU2_CN4 UPC_NEXT7 UPC_NEXT6 UPC_NEXT5 UPC_NEXT4 74LS181
xU3 UPC8 UPC9 UPC10 UPC11 B8 B9 B10 B11 NETU1_CN NETU3_S1 NETU3_S2 NETU1_CN NETU2_CN4 NETU3_M NETU3_^G NETU3_^P NETU3_AEQB NETU3_CN4 UPC_NEXT11 UPC_NEXT10 UPC_NEXT9 UPC_NEXT8 74LS181
xU4 UPC12 UPC13 UPC14 UPC15 B12 B13 B14 B15 NETU1_CN NETU4_S1 NETU4_S2 NETU1_CN NETU3_CN4 NETU4_M NETU4_^G NETU4_^P NETU4_AEQB NETU4_CN4 UPC_NEXT15 UPC_NEXT14 UPC_NEXT13 UPC_NEXT12 74LS181
.subckt 74LS181 ^A0 ^A1 ^A2 ^A3 ^B0 ^B1 ^B2 ^B3 S0 S1 S2 S3 CN M ^G ^P AEQB CN4 ^F3 ^F2 ^F1 ^F0
aU1 [ ^B3 S3 ^A3] NetU1_4 AND3
aU2 [ ^A3 S2 NetU2_3] NetU2_4 AND3
aU9 [ NetU10_1 NetU10_2 NetU28_2] NetU14_3 AND3
aU19 [ ^B2 S3 ^A2] NetU19_4 AND3
aU20 [ ^A2 S2 NetU20_3] NetU20_4 AND3
aU28 [ NetU10_2 NetU28_2 NetU26_5] NetU28_4 AND3
aU33 [ ^B1 S3 ^A1] NetU33_4 AND3
aU34 [ ^A1 S2 NetU34_3] NetU34_4 AND3
aU41 [ NetU10_3 NetU10_4 NetU26_5] NetU41_4 AND3
aU46 [ ^B0 S3 ^A0] NetU46_4 AND3
aU47 [ ^A0 S2 NetU47_3] NetU47_4 AND3
aU54 [ CN NetU11_4 NetU26_5] NetU54_4 AND3
.model AND3 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU3 [ NetU1_4 NetU2_4] NetU10_1 NOR
aU23 [ NetU19_4 NetU20_4] NetU10_2 NOR
aU37 [ NetU33_4 NetU34_4] NetU10_3 NOR
aU52 [ NetU46_4 NetU47_4] NetU11_4 NOR
aU57 [ NetU54_4 NetU55_3] NetU45_2 NOR
.model NOR d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU4 [ NetU2_3 S1] NetU4_3 AND
aU5 [ S0 ^B3] NetU5_3 AND
aU6 [ NetU10_1 NetU24_4] NetU14_2 AND
aU21 [ NetU20_3 S1] NetU21_3 AND
aU22 [ S0 ^B2] NetU22_3 AND
aU29 [ NetU24_4 NetU26_5] NetU29_3 AND
aU35 [ NetU34_3 S1] NetU35_3 AND
aU36 [ S0 ^B1] NetU36_3 AND
aU42 [ NetU28_2 NetU26_5] NetU42_3 AND
aU48 [ NetU47_3 S1] NetU48_3 AND
aU49 [ S0 ^B0] NetU49_3 AND
aU55 [ NetU10_4 NetU26_5] NetU55_3 AND
.model AND d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU7 [ NetU4_3 NetU5_3 ^A3] NetU13_2 NOR3
aU24 [ NetU21_3 NetU22_3 ^A2] NetU24_4 NOR3
aU38 [ NetU35_3 NetU36_3 ^A1] NetU28_2 NOR3
aU44 [ NetU40_5 NetU41_4 NetU42_3] NetU31_2 NOR3
aU51 [ NetU48_3 NetU49_3 ^A0] NetU10_4 NOR3
.model NOR3 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU8 ^B3 NetU2_3 NOT
aU15 ^G NetU15_2 NOT
aU17 NetU11_6 NetU16_2 NOT
aU25 ^B2 NetU20_3 NOT
aU39 ^B1 NetU34_3 NOT
aU50 ^B0 NetU47_3 NOT
aU56 M NetU26_5 NOT
.model NOT d_inverter(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU10 [ NetU10_1 NetU10_2 NetU10_3 NetU10_4] NetU10_5 AND4
aU27 [ NetU10_3 NetU10_2 NetU10_4 NetU26_5] NetU27_5 AND4
aU40 [ CN NetU11_4 NetU10_3 NetU26_5] NetU40_5 AND4
aU60 [ ^F3 ^F2 ^F1 ^F0] AEQB AND4
.model AND4 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU11 [ NetU10_1 NetU10_2 NetU10_3 NetU11_4 CN] NetU11_6 NAND5
.model NAND5 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU12 [ NetU10_1 NetU10_2 NetU10_3 NetU11_4] ^P NAND4
.model NAND4 d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU13 [ NetU10_1 NetU13_2] NetU13_3 XOR
aU18 [ NetU13_3 NetU18_2] ^F3 XOR
aU30 [ NetU10_2 NetU24_4] NetU30_3 XOR
aU31 [ NetU30_3 NetU31_2] ^F2 XOR
aU43 [ NetU10_3 NetU28_2] NetU43_3 XOR
aU45 [ NetU43_3 NetU45_2] ^F1 XOR
aU53 [ NetU11_4 NetU10_4] NetU53_3 XOR
aU59 [ NetU53_3 NetU58_3] ^F0 XOR
.model XOR d_xor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU14 [ NetU13_2 NetU14_2 NetU14_3 NetU10_5] ^G NOR4
aU32 [ NetU26_6 NetU27_5 NetU28_4 NetU29_3] NetU18_2 NOR4
.model NOR4 d_nor(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU16 [ NetU15_2 NetU16_2] CN4 OR
.model OR d_or(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU26 [ CN NetU11_4 NetU10_3 NetU10_2 NetU26_5] NetU26_6 AND5
.model AND5 d_and(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
aU58 [ CN NetU26_5] NetU58_3 NAND
.model NAND d_nand(rise_delay = 1e-9 fall_delay = 1e-9 input_load = 1e-3)
.ends
xU5 NETU1_CN CONSTANT1
xU6 B2 CONSTANT1
.subckt CONSTANT1 constant1
VV1 Net1_1 0 DC 3.5
a1 [Net1_1] [constant1] ADC
.model ADC adc_bridge(in_low = 0.3 in_high = 1)
.ends
.ends
您添加了 0 人 到此讨论。请谨慎行事。
请先完成此评论的编辑！
请 注册 或者 后发表评论