Initial commit

348288ca · 赵鹏翀 · 348288ca · 348288ca · 348288ca · 348288ca
--- a/.gitignore
+++ b/.gitignore
+*.cir
+*.xml
+*.bak
+/.vs
\ No newline at end of file
--- a/2mux1.dlsche
+++ b/2mux1.dlsche
--- a/2mux1.dlsche.svg
+++ b/2mux1.dlsche.svg
--- a/4mux1.dlsche
+++ b/4mux1.dlsche
--- a/4mux1.dlsche.svg
+++ b/4mux1.dlsche.svg
--- a/8signto16.dlsche
+++ b/8signto16.dlsche
--- a/8signto16.dlsche.svg
+++ b/8signto16.dlsche.svg
--- a/MIPS.dlsche
+++ b/MIPS.dlsche
--- a/MIPS.dlsche.svg
+++ b/MIPS.dlsche.svg
--- a/README.md
+++ b/README.md
+# 说明
+16 位 MIPS 多周期微处理器
+# 原理图
+![raw svg](MIPS.dlsche.svg)
--- a/al.dlsche
+++ b/al.dlsche
--- a/al.dlsche.svg
+++ b/al.dlsche.svg
--- a/alu.dlsche
+++ b/alu.dlsche
--- a/alu.dlsche.svg
+++ b/alu.dlsche.svg
--- a/fsm.dlsche
+++ b/fsm.dlsche
--- a/fsm.dlsche.svg
+++ b/fsm.dlsche.svg
--- a/mips-multi-cycle.dlproj
+++ b/mips-multi-cycle.dlproj
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project id="73bfb951-3609-4a62-8c77-b373026f1088" name="mips-multi-cycle" version="1">
+
+  <files>
+    <filefolder id="c0a181af-d67c-4dd0-9275-aa277475c77c" name="子模块">
+      <file relativepath="2mux1.dlsche"/>
+      <file relativepath="4mux1.dlsche"/>
+      <file relativepath="alu.dlsche"/>
+      <file relativepath="regdst_mux.dlsche"/>
+      <file relativepath="al.dlsche"/>
+      <file relativepath="8signto16.dlsche"/>
+      <file relativepath="reg.dlsche"/>
+      <file relativepath="fsm.dlsche"/>
+      <file relativepath="multi_mux.dlsche"/>
+    </filefolder>
+    <filefolder id="2156f6c8-84d5-409f-859c-fddce752753a" name="存储器映射文件">
+      <file relativepath="ram.rxm"/>
+    </filefolder>
+    <filefolder id="3463ada9-1cc7-4838-ab12-f98af0a12bf2" name="源程序文件">
+      <file relativepath="ram.asm"/>
+      <file relativepath="ram.bat"/>
+    </filefolder>
+    <file relativepath="MIPS.dlsche"/>
+    <file relativepath="README.md"/>
+  </files>
+
+</project>
--- a/mipsasm.exe
+++ b/mipsasm.exe
--- a/mipsmasm.c
+++ b/mipsmasm.c
--- a/multi_mux.dlsche
+++ b/multi_mux.dlsche
--- a/multi_mux.dlsche.svg
+++ b/multi_mux.dlsche.svg
--- a/ram.asm
+++ b/ram.asm
+.text
+
+addi $r2, $r0, 5         ;r2 = r0 + 5
+addi $r3, $r0, 12        ;r3 = r0 + 12
+addi $r1, $r3, -9        ;r1 = r3 + (-9)
+
+or  $r3, $r0, $r1        ;r3 = r0 | r1
+and $r2, $r2, $r3        ;r2 = r2 & r3
+add $r3, $r3, $r1        ;r3 = r3 + r1
+
+beq  $r1, $r3, end       ;if r1 == r3, goto end
+slt  $r3, $r2, $r3       ;r3 = r2 < r3 ? 1 : 0
+andi $r3, $r3, 0         ;r3 = r3 & 0
+andi $r0, $r1, 0         ;r0 = r1 & 0
+
+beq  $r3, $r0, F1        ;if r3 == r0, goto F1
+addi $r0, $r1, 0         ;r0 = r1 + 0
+
+end:
+sw   $r2, 84($r0)        ;mem[r0+84] = r2
+sllv $r1, $r1, $r0       ;r1 = r1 << r0
+bne  $r1, $r2, NEXT      ;if r1 != r2, goto NEXT  
+
+F1:
+slt $r3, $r1, $r2        ;r3 = r1 < r2 ? 1 : 0
+add $r3, $r2, $r1        ;r3 = r2 + r1
+sub $r2, $r2, $r0        ;r2 = r2 - r0
+sw  $r3, 68($r3)         ;mem[r3+68] = r3
+lw  $r3, 80($r0)         ;r3 = mem[r0+80]
+jump end                 ;goto end
+addi $r2, $r0, 1         ;r2 = r0 + 1         
+
+NEXT:
+sub $r1, $r1, $r0        ;r1 = r1 - r0 
+add $r1, $r1, $r0        ;r1 = r1 + r0  
+
+sllv $r3, $r0, $r1       ;r3 = r0 << r1    
+
+ori  $r1, $r1, 3         ;r1 = r1 | 3
+srav $r3, $r3, $r1       ;r3 = r3 >> r1   
+andi $r1, $r2, 4         ;r1 = r2 + 4 
+
+  
+    
+
+
--- a/ram.bat
+++ b/ram.bat
+@echo off
+mipsasm.exe ram.asm -o ram.rxm -l ram.lst -g ram.dbg
+pause
--- a/ram.dbg
+++ b/ram.dbg
--- a/ram.lst
+++ b/ram.lst
+0001                  .text
+0002                  
+0003    00    52 05   addi $r2, $r0, 5         ;r2 = r0 + 5
+0004    02    53 0C   addi $r3, $r0, 12        ;r3 = r0 + 12
+0005    04    5D F7   addi $r1, $r3, -9        ;r1 = r3 + (-9)
+0006                  
+0007    06    01 C0   or  $r3, $r0, $r1        ;r3 = r0 | r1
+0008    08    0B 81   and $r2, $r2, $r3        ;r2 = r2 & r3
+0009    0A    0D C2   add $r3, $r3, $r1        ;r3 = r3 + r1
+0010                  
+0011    0C    87 05   beq  $r1, $r3, end       ;if r1 == r3, goto end
+0012    0E    0B C7   slt  $r3, $r2, $r3       ;r3 = r2 < r3 ? 1 : 0
+0013    10    4F 00   andi $r3, $r3, 0         ;r3 = r3 & 0
+0014    12    44 00   andi $r0, $r1, 0         ;r0 = r1 & 0
+0015                  
+0016    14    8C 04   beq  $r3, $r0, F1        ;if r3 == r0, goto F1
+0017    16    54 00   addi $r0, $r1, 0         ;r0 = r1 + 0
+0018                  
+0019                  end:
+0020    18    72 54   sw   $r2, 84($r0)        ;mem[r0+84] = r2
+0021    1A    04 44   sllv $r1, $r1, $r0       ;r1 = r1 << r0
+0022    1C    96 07   bne  $r1, $r2, NEXT      ;if r1 != r2, goto NEXT  
+0023                  
+0024                  F1:
+0025    1E    06 C7   slt $r3, $r1, $r2        ;r3 = r1 < r2 ? 1 : 0
+0026    20    09 C2   add $r3, $r2, $r1        ;r3 = r2 + r1
+0027    22    08 83   sub $r2, $r2, $r0        ;r2 = r2 - r0
+0028    24    7F 44   sw  $r3, 68($r3)         ;mem[r3+68] = r3
+0029    26    63 50   lw  $r3, 80($r0)         ;r3 = mem[r0+80]
+0030    28    B0 0C   jump end                 ;goto end
+0031    2A    52 01   addi $r2, $r0, 1         ;r2 = r0 + 1         
+0032                  
+0033                  NEXT:
+0034    2C    04 43   sub $r1, $r1, $r0        ;r1 = r1 - r0 
+0035    2E    04 42   add $r1, $r1, $r0        ;r1 = r1 + r0  
+0036                  
+0037    30    01 C4   sllv $r3, $r0, $r1       ;r3 = r0 << r1    
+0038                  
+0039    32    35 03   ori  $r1, $r1, 3         ;r1 = r1 | 3
+0040    34    0D C6   srav $r3, $r3, $r1       ;r3 = r3 >> r1   
+0041    36    49 04   andi $r1, $r2, 4         ;r1 = r2 + 4 
+0042                  
+0043                    
+0044                      
+0045                  
+0046                  
--- a/ram.rxm
+++ b/ram.rxm
--- a/reg.dlsche
+++ b/reg.dlsche
--- a/reg.dlsche.svg
+++ b/reg.dlsche.svg
--- a/regdst_mux.dlsche
+++ b/regdst_mux.dlsche
--- a/regdst_mux.dlsche.svg
+++ b/regdst_mux.dlsche.svg