• rsc's avatar
    Apparently the initial interrupt count lapic[TICR] · d5596cd6
    rsc 提交于
    must be set *after* initializing the lapic[TIMER] vector.
    
    Doing this, we now get clock interrupts on cpu 1.
    (No idea why we always got them on cpu 0.)
    
    Don't write to TCCR - it is read-only.
    d5596cd6
defs.h 4.1 KB