x86-64 bits and instructions for performance counters.

104d3497 · Silas Boyd-Wickizer · 1b204a5b · 104d3497 · 104d3497
--- a/amd64.h
+++ b/amd64.h
 #pragma once
 // Routines to let C code use special x86 instructions.

+static inline void
+cpuid(u32 info, u32 *eaxp, u32 *ebxp,
+      u32 *ecxp, u32 *edxp)
+{
+  u32 eax, ebx, ecx, edx;
+  __asm volatile("cpuid" 
+                 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx)
+                 : "a" (info));
+  if (eaxp)
+    *eaxp = eax;
+  if (ebxp)
+    *ebxp = ebx;
+  if (ecxp)
+    *ecxp = ecx;
+  if (edxp)
+    *edxp = edx;
+}
+
 static inline u8
 inb(u16 port)
 {
@@ -127,14 +145,23 @@ writemsr(u32 msr, u64 val)
  __asm volatile("wrmsr" : : "c" (msr), "a" (lo), "d" (hi));
 }

-static inline
-u64 rdtsc(void)
+static inline u64
+rdtsc(void)
 {
  u32 hi, lo;
  __asm volatile("rdtsc" : "=a"(lo), "=d"(hi));
  return ((u64)lo)|(((u64)hi)<<32);
 }

+static inline u64
+rdpmc(u32 ecx)
+{
+  u32 hi, lo;
+  __asm volatile("rdpmc" : "=a" (lo), "=d" (hi) : "c" (ecx));
+  return ((u64) lo) | (((u64) hi) << 32);
+}
+
+
 static inline
 void hlt(void)
 {
@@ -150,6 +177,20 @@ rrsp(void)
 }

 static inline void
+lcr4(u64 val)
+{
+  __asm volatile("movq %0,%%cr4" : : "r" (val));
+}
+
+static inline u64
+rcr4(void)
+{
+  u64 val;
+  __asm volatile("movq %%cr4,%0" : "=r" (val));
+  return val;
+}
+
+static inline void
 lcr3(u64 val)
 {
  __asm volatile("movq %0,%%cr3" : : "r" (val));

--- a/bits.h
+++ b/bits.h
@@ -39,6 +39,8 @@
 #define CR0_CD		0x40000000	// Cache Disable
 #define CR0_PG		0x80000000	// Paging

+#define CR4_PCE         0x100           // RDPMC at CPL > 0
+
 // FS/GS base registers
 #define MSR_FS_BASE     0xc0000100
 #define MSR_GS_BASE     0xc0000101
@@ -48,3 +50,21 @@
 #define MSR_LSTAR       0xc0000082
 #define MSR_CSTAR       0xc0000083
 #define MSR_SFMASK      0xc0000084
+
+// AMD performance event-select registers
+#define MSR_AMD_PERF_SEL0  0xC0010000
+#define MSR_AMD_PERF_SEL1  0xC0010001
+#define MSR_AMD_PERF_SEL2  0xC0010002
+#define MSR_AMD_PERF_SEL3  0xC0010003
+// AMD performance event-count registers
+#define MSR_AMD_PERF_CNT0  0xC0010004
+#define MSR_AMD_PERF_CNT1  0xC0010005
+#define MSR_AMD_PERF_CNT2  0xC0010006
+#define MSR_AMD_PERF_CNT3  0xC0010007
+
+// Intel performance event-select registers
+#define MSR_INTEL_PERF_SEL0 0x00000186
+#define MSR_INTEL_PERF_SEL1 0x00000187
+// Intel performance event-count registers
+#define MSR_INTEL_PERF_CNT0 0x000000c1
+#define MSR_INTEL_PERF_CNT1 0x000000c2