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提交 b31a215b 创建 作者: Silas Boyd-Wickizer's avatar Silas Boyd-Wickizer
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lapic.c to 64-bit and the necessary parts of kalloc.c and vm.c.

上级 a5f0d190
隐藏空白字符变更
内嵌 并排
正在显示 包含 113 行增加 和 267 行删除
Makefile
浏览文件 @ b31a215b
......@@ -5,11 +5,13 @@ OBJS = \
cga.o \
console.o \
lapic.o \
kalloc.o \
main.o \
mp.o \
spinlock.o \
string.o \
uart.o \
vm.o \
trap.o
# Cross-compiling (e.g., on Mac OS X)
......
bits.h
浏览文件 @ b31a215b
// Rflags register
// Eflags register
#define FL_CF 0x00000001 // Carry Flag
#define FL_PF 0x00000004 // Parity Flag
#define FL_AF 0x00000010 // Auxiliary carry Flag
......@@ -20,3 +20,21 @@
#define FL_VIF 0x00080000 // Virtual Interrupt Flag
#define FL_VIP 0x00100000 // Virtual Interrupt Pending
#define FL_ID 0x00200000 // ID flag
// Page fault error codes
#define FEC_PR 0x1 // Page fault caused by protection violation
#define FEC_WR 0x2 // Page fault caused by a write
#define FEC_U 0x4 // Page fault occured while in user mode
// Control Register flags
#define CR0_PE 0x00000001 // Protection Enable
#define CR0_MP 0x00000002 // Monitor coProcessor
#define CR0_EM 0x00000004 // Emulation
#define CR0_TS 0x00000008 // Task Switched
#define CR0_ET 0x00000010 // Extension Type
#define CR0_NE 0x00000020 // Numeric Errror
#define CR0_WP 0x00010000 // Write Protect
#define CR0_AM 0x00040000 // Alignment Mask
#define CR0_NW 0x20000000 // Not Writethrough
#define CR0_CD 0x40000000 // Cache Disable
#define CR0_PG 0x80000000 // Paging
boot.S
浏览文件 @ b31a215b
......@@ -134,7 +134,7 @@ start32:
movl %eax, %cr4
# Load CR3 with physical base address of level 4 page table.
movl $PADDR(pml4), %eax
movl $PADDR(kpml4), %eax
movl %eax, %cr3
# Enable IA-32e mode by setting IA32_EFER.LME = 1.
......@@ -175,7 +175,7 @@ start64hi:
# Load VA stack pointer
movabsq $(stack+STACK), %rsp
# Kill 1GB identity mapping
movq $0, pml4
movq $0, kpml4
# Clear frame pointer for stack walks, and call into C code.
movq $0, %rbp
call cmain
......@@ -270,8 +270,8 @@ colorbar:
# This would be easier if we could use the PS bit to create GB-sized entries
# and skip the pdt table, but not all chips support it, and QEMU doesn't.
.align 4096
.global pml4
pml4:
.global kpml4
kpml4:
.quad PADDR(pdpt0) + (1<<0) + (1<<1) // present, read/write
.space 4096 - 16
.quad PADDR(pdpt1) + (1<<0) + (1<<1) // present, read/write
......
kalloc.c
浏览文件 @ b31a215b
......@@ -3,27 +3,16 @@
// and pipe buffers. Allocates 4096-byte pages.
#include "types.h"
#include "defs.h"
#include "param.h"
#include "memlayout.h"
#include "mmu.h"
#include "spinlock.h"
#include "condvar.h"
#include "queue.h"
#include "proc.h"
#include "kalloc.h"
#include "xv6-mtrace.h"
#include "kernel.h"
void kminit(void);
struct kmem kmems[NCPU];
extern char end[]; // first address after kernel loaded from ELF file
char *newend;
enum { kalloc_memset = 0 };
static int kinited __attribute__ ((aligned (CACHELINE)));
// simple page allocator to get off the ground during boot
char *
pgalloc(void)
......@@ -31,12 +20,13 @@ pgalloc(void)
if (newend == 0)
newend = end;
void *p = (void*)PGROUNDUP((uint)newend);
void *p = (void*)PGROUNDUP((uptr)newend);
memset(p, 0, PGSIZE);
newend = newend + PGSIZE;
return p;
}
#if 0
static void __attribute__((unused))
kmemprint(void)
{
......@@ -276,3 +266,4 @@ kmalloc(uint nbytes)
RET_EIP());
return r;
}
#endif
kernel.h
浏览文件 @ b31a215b
#define KBASE 0xFFFFFFFF80000000ull
#define PGSIZE (2*1024*1024ull)
#define PBASE 0xFFFFFF0000000000ull
#define KCSEG (2<<3) /* kernel code segment */
#define KDSEG (3<<3) /* kernel data segment */
......
lapic.c
浏览文件 @ b31a215b
......@@ -39,7 +39,7 @@
#define TCCR (0x0390/4) // Timer Current Count
#define TDCR (0x03E0/4) // Timer Divide Configuration
volatile u32 *lapic = (u32 *)(KBASE + 0xfee00000);
volatile u32 *lapic = (u32 *)(PBASE + 0xfee00000);
static void
lapicw(int index, int value)
......
main.c
浏览文件 @ b31a215b
......@@ -8,6 +8,7 @@ extern void initconsole(void);
extern void initmp(void);
extern void initlapic(void);
extern void inittrap(void);
extern void initpg(void);
void
cmain(void)
......@@ -15,6 +16,7 @@ cmain(void)
inituart();
initcga();
initconsole();
initpg();
initmp();
initlapic();
#if 0
......
memlayout.h
浏览文件 @ b31a215b
// Memory layout
#define PGSIZE 4096 // bytes mapped by a page
#define PGSHIFT 12 // log2(PGSIZE)
#define KSTKSIZE (8*PGSIZE) // size of a kernel stack
#define IOSPACEB 0xA0000 // begin IO space
#define IOSPACEE 0x100000 // end IO space
#define PHYSTOP 0xE000000 // use phys mem up to here as free pool
#define KERNBASE 0xF0000000
#define USERTOP (KERNBASE-PGSIZE)
#define KERNLINK 0xF0100000
#ifndef __ASSEMBLER__
static inline uint v2p(void *a) { return (uint) a - KERNBASE; }
static inline void *p2v(uint a) { return (void *) a + KERNBASE; }
#endif
#define V2P(a) ((uint) a - KERNBASE)
#define P2V(a) ((void *) a + KERNBASE)
#define PHYSTOP 0xE000000 // use phys mem up to here as free pool
mmu.h
浏览文件 @ b31a215b
// This file contains definitions for the
// x86 memory management unit (MMU).
#define PGSIZE 4096
#define PGSHIFT 12 // log2(PGSIZE)
// Eflags register
#define FL_CF 0x00000001 // Carry Flag
#define FL_PF 0x00000004 // Parity Flag
#define FL_AF 0x00000010 // Auxiliary carry Flag
#define FL_ZF 0x00000040 // Zero Flag
#define FL_SF 0x00000080 // Sign Flag
#define FL_TF 0x00000100 // Trap Flag
#define FL_IF 0x00000200 // Interrupt Enable
#define FL_DF 0x00000400 // Direction Flag
#define FL_OF 0x00000800 // Overflow Flag
#define FL_IOPL_MASK 0x00003000 // I/O Privilege Level bitmask
#define FL_IOPL_0 0x00000000 // IOPL == 0
#define FL_IOPL_1 0x00001000 // IOPL == 1
#define FL_IOPL_2 0x00002000 // IOPL == 2
#define FL_IOPL_3 0x00003000 // IOPL == 3
#define FL_NT 0x00004000 // Nested Task
#define FL_RF 0x00010000 // Resume Flag
#define FL_VM 0x00020000 // Virtual 8086 mode
#define FL_AC 0x00040000 // Alignment Check
#define FL_VIF 0x00080000 // Virtual Interrupt Flag
#define FL_VIP 0x00100000 // Virtual Interrupt Pending
#define FL_ID 0x00200000 // ID flag
// Page fault error codes
#define FEC_PR 0x1 // Page fault caused by protection violation
#define FEC_WR 0x2 // Page fault caused by a write
#define FEC_U 0x4 // Page fault occured while in user mode
// Control Register flags
#define CR0_PE 0x00000001 // Protection Enable
#define CR0_MP 0x00000002 // Monitor coProcessor
#define CR0_EM 0x00000004 // Emulation
#define CR0_TS 0x00000008 // Task Switched
#define CR0_ET 0x00000010 // Extension Type
#define CR0_NE 0x00000020 // Numeric Errror
#define CR0_WP 0x00010000 // Write Protect
#define CR0_AM 0x00040000 // Alignment Mask
#define CR0_NW 0x20000000 // Not Writethrough
#define CR0_CD 0x40000000 // Cache Disable
#define CR0_PG 0x80000000 // Paging
//PAGEBREAK!
// Segment Descriptor
struct segdesc {
uint lim_15_0 : 16; // Low bits of segment limit
uint base_15_0 : 16; // Low bits of segment base address
uint base_23_16 : 8; // Middle bits of segment base address
uint type : 4; // Segment type (see STS_ constants)
uint s : 1; // 0 = system, 1 = application
uint dpl : 2; // Descriptor Privilege Level
uint p : 1; // Present
uint lim_19_16 : 4; // High bits of segment limit
uint avl : 1; // Unused (available for software use)
uint rsv1 : 1; // Reserved
uint db : 1; // 0 = 16-bit segment, 1 = 32-bit segment
uint g : 1; // Granularity: limit scaled by 4K when set
uint base_31_24 : 8; // High bits of segment base address
};
// Normal segment
#define SEG(type, base, lim, dpl) (struct segdesc) \
{ ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff, \
((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \
(uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 }
#define SEG16(type, base, lim, dpl) (struct segdesc) \
{ (lim) & 0xffff, (uint)(base) & 0xffff, \
((uint)(base) >> 16) & 0xff, type, 1, dpl, 1, \
(uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 }
#define DPL_USER 0x3 // User DPL
// Application segment type bits
#define STA_X 0x8 // Executable segment
#define STA_E 0x4 // Expand down (non-executable segments)
#define STA_C 0x4 // Conforming code segment (executable only)
#define STA_W 0x2 // Writeable (non-executable segments)
#define STA_R 0x2 // Readable (executable segments)
#define STA_A 0x1 // Accessed
// System segment type bits
#define STS_T16A 0x1 // Available 16-bit TSS
#define STS_LDT 0x2 // Local Descriptor Table
#define STS_T16B 0x3 // Busy 16-bit TSS
#define STS_CG16 0x4 // 16-bit Call Gate
#define STS_TG 0x5 // Task Gate / Coum Transmitions
#define STS_IG16 0x6 // 16-bit Interrupt Gate
#define STS_TG16 0x7 // 16-bit Trap Gate
#define STS_T32A 0x9 // Available 32-bit TSS
#define STS_T32B 0xB // Busy 32-bit TSS
#define STS_CG32 0xC // 32-bit Call Gate
#define STS_IG32 0xE // 32-bit Interrupt Gate
#define STS_TG32 0xF // 32-bit Trap Gate
// A linear address 'la' has a three-part structure as follows:
//
// +--------10------+-------10-------+---------12----------+
// | Page Directory | Page Table | Offset within Page |
// | Index | Index | |
// +----------------+----------------+---------------------+
// \--- PDX(la) --/ \--- PTX(la) --/
// page directory index
#define PDX(la) (((uint)(la) >> PDXSHIFT) & 0x3FF)
#define PTXSHIFT 12 // offset of PTX in a linear address
#define PDXSHIFT 21 // offset of PDX in a linear address
#define PDPXSHIFT 30 // offset of PDPX in a linear address
#define PML4XSHIFT 39 // offset of PML4X in a linear address
// page table index
#define PTX(la) (((uint)(la) >> PTXSHIFT) & 0x3FF)
#define PTX(la) (((uptr)(la) >> PTXSHIFT) & 0x1FF)
// construct linear address from indexes and offset
#define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
// Page directory and page table constants.
#define NPDENTRIES 1024 // page directory entries per page directory
#define NPTENTRIES 1024 // page table entries per page table
// page directory index
#define PDX(la) (((uptr)(la) >> PDXSHIFT) & 0x1FF)
#define PTXSHIFT 12 // offset of PTX in a linear address
#define PDXSHIFT 22 // offset of PDX in a linear address
// page diretory pointer index
#define PDPX(la) (((uptr)(la) >> PDPXSHIFT) & 0x1FF)
#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
#define PGROUNDDOWN(a) ((__typeof__(a))((((unsigned int)(a)) & ~(PGSIZE-1))))
// page map level 4 index
#define PML4X(la) (((uptr)(la) >> PML4XSHIFT) & 0x1FF)
// Page table/directory entry flags.
#define PTE_P 0x001 // Present
......@@ -134,84 +30,8 @@ struct segdesc {
#define PTE_MBZ 0x180 // Bits must be zero
#define PTE_COW 0x800 // copy-on-write
// Address in page table or page directory entry
#define PTE_ADDR(pte) ((uint)(pte) & ~0xFFF)
typedef uint pte_t;
// Task state segment format
struct taskstate {
uint link; // Old ts selector
uint esp0; // Stack pointers and segment selectors
ushort ss0; // after an increase in privilege level
ushort padding1;
uint *esp1;
ushort ss1;
ushort padding2;
uint *esp2;
ushort ss2;
ushort padding3;
void *cr3; // Page directory base
uint *eip; // Saved state from last task switch
uint eflags;
uint eax; // More saved state (registers)
uint ecx;
uint edx;
uint ebx;
uint *esp;
uint *ebp;
uint esi;
uint edi;
ushort es; // Even more saved state (segment selectors)
ushort padding4;
ushort cs;
ushort padding5;
ushort ss;
ushort padding6;
ushort ds;
ushort padding7;
ushort fs;
ushort padding8;
ushort gs;
ushort padding9;
ushort ldt;
ushort padding10;
ushort t; // Trap on task switch
ushort iomb; // I/O map base address
};
// PAGEBREAK: 12
// Gate descriptors for interrupts and traps
struct gatedesc {
uint off_15_0 : 16; // low 16 bits of offset in segment
uint cs : 16; // code segment selector
uint args : 5; // # args, 0 for interrupt/trap gates
uint rsv1 : 3; // reserved(should be zero I guess)
uint type : 4; // type(STS_{TG,IG32,TG32})
uint s : 1; // must be 0 (system)
uint dpl : 2; // descriptor(meaning new) privilege level
uint p : 1; // Present
uint off_31_16 : 16; // high bits of offset in segment
};
// Set up a normal interrupt/trap gate descriptor.
// - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
// interrupt gate clears FL_IF, trap gate leaves FL_IF alone
// - sel: Code segment selector for interrupt/trap handler
// - off: Offset in code segment for interrupt/trap handler
// - dpl: Descriptor Privilege Level -
// the privilege level required for software to invoke
// this interrupt/trap gate explicitly using an int instruction.
#define SETGATE(gate, istrap, sel, off, d) \
{ \
(gate).off_15_0 = (uint)(off) & 0xffff; \
(gate).cs = (sel); \
(gate).args = 0; \
(gate).rsv1 = 0; \
(gate).type = (istrap) ? STS_TG32 : STS_IG32; \
(gate).s = 0; \
(gate).dpl = (d); \
(gate).p = 1; \
(gate).off_31_16 = (uint)(off) >> 16; \
}
#define PGROUNDUP(sz) (((sz)+PGSIZE-1) & ~(PGSIZE-1))
#define PGROUNDDOWN(a) ((__typeof__(a))((((uptr)(a)) & ~(PGSIZE-1))))
// Address in page table or page directory entry
#define PTE_ADDR(pte) ((uptr)(pte) & ~0xFFF)
types.h
浏览文件 @ b31a215b
......@@ -13,4 +13,9 @@ typedef uint64 u64;
typedef uint64 uptr;
typedef uptr paddr;
typedef u64 pml4e_t;
typedef u64 pdpe_t;
typedef u64 pde_t;
typedef u64 pte_t;
#define __mpalign__ __attribute__((aligned(CACHELINE)))
vm.c
浏览文件 @ b31a215b
#include "param.h"
#include "types.h"
#include "defs.h"
#include "x86.h"
#include "memlayout.h"
#include "mmu.h"
#include "spinlock.h"
#include "condvar.h"
#include "queue.h"
#include "proc.h"
#include "elf.h"
#include "kalloc.h"
#include "kernel.h"
#include "memlayout.h"
extern char data[]; // defined in data.S
static pde_t *kpgdir __attribute__ ((aligned (CACHELINE))); // for use in scheduler()
extern pml4e_t kpml4[];
struct segdesc gdt[NSEGS];
extern char* pgalloc(void);
#if 0
// page map for during boot
// XXX build a static page table in assembly
static void
......@@ -43,37 +38,66 @@ pgmap(void *va, void *last, uint pa)
pa += PGSIZE;
}
}
#endif
// set up a page table to get off the ground
void
pginit(char* (*alloc)(void))
static void
pgmap(void *va, void *last, paddr pa)
{
uint cr0;
pml4e_t *pml4;
pml4e_t pml4e;
pdpe_t *pdp;
pdpe_t pdpe;
pde_t *pd;
pde_t pde;
pte_t *pt;
kpgdir = (pde_t *) alloc();
pgmap((void *) 0, (void *) PHYSTOP, 0);
pgmap((void *) KERNBASE, (void *) (KERNBASE+PHYSTOP), 0);
pgmap((void*)0xFE000000, 0, 0xFE000000);
for(;;){
pml4 = &kpml4[PML4X(va)];
pml4e = *pml4;
if (pml4e == 0) {
pdp = (pdpe_t *) pgalloc();
*pml4 = v2p(pdp) | PTE_P | PTE_W;
} else {
pdp = (pdpe_t*)p2v(PTE_ADDR(pml4e));
}
switchkvm(); // load kpgdir into cr3
pdp = &pdp[PDPX(va)];
pdpe = *pdp;
if (pdpe == 0) {
pd = (pde_t *) pgalloc();
*pdp = v2p(pd) | PTE_P | PTE_W;
} else {
pd = (pde_t*)p2v(PTE_ADDR(pdpe));
}
cr0 = rcr0();
cr0 |= CR0_PG;
lcr0(cr0); // paging on
pd = &pd[PDX(va)];
pde = *pd;
if (pde == 0) {
pt = (pte_t *) pgalloc();
*pd = v2p(pt) | PTE_P | PTE_W;
} else {
pt = (pde_t*)p2v(PTE_ADDR(pde));
}
// new gdt
gdt[SEG_KCODE] = SEG(STA_X|STA_R, 0, 0xffffffff, 0);
gdt[SEG_KDATA] = SEG(STA_W, 0, 0xffffffff, 0);
lgdt((void *)v2p(gdt), sizeof(gdt));
loadgs(SEG_KDATA << 3);
loadfs(SEG_KDATA << 3);
loades(SEG_KDATA << 3);
loadds(SEG_KDATA << 3);
loadss(SEG_KDATA << 3);
pt = &pt[PTX(va)];
*pt = pa | PTE_W | PTE_P;
if(va == last)
break;
va += PGSIZE;
pa += PGSIZE;
}
}
__asm volatile("ljmp %0,$1f\n 1:\n" :: "i" (SEG_KCODE << 3)); // reload cs
// set up a page table to get off the ground
void
initpg(char* (*alloc)(void))
{
pgmap((void *) 0, (void *) PHYSTOP, 0);
pgmap((void *) PBASE, (void *) (PBASE+(1UL<<32)), 0);
//switchkvm(); // load kpgdir into cr3
}
#if 0
// Set up CPU's kernel segment descriptors.
// Run once at boot time on each CPU.
void
......@@ -900,3 +924,4 @@ pagefault(struct vmap *vmap, uint va, uint err)
rcu_end_read();
return 1;
}
#endif
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