kill TLB shoot down code

b738a4f1 · Frans Kaashoek · de40730d · b738a4f1 · b738a4f1 · b738a4f1
--- a/defs.h
+++ b/defs.h
@@ -73,7 +73,6 @@ int             cpunum(void);
 extern volatile uint*    lapic;
 void            lapiceoi(void);
 void            lapicinit(int);
-void            lapic_tlbflush(uint);
 void            lapicstartap(uchar, uint);
 void            microdelay(int);


--- a/lapic.c
+++ b/lapic.c
@@ -47,27 +47,6 @@ lapicw(int index, int value)
  lapic[ID];  // wait for write to finish, by reading
 }

-static uint
-lapicr(uint off)
-{
-  return lapic[off];
-}
-
-static int
-apic_icr_wait()
-{
-    uint i = 100000;
-    while ((lapicr(ICRLO) & BUSY) != 0) {
-        nop_pause();
-        i--;
-        if (i == 0) {
-            cprintf("apic_icr_wait: wedged?\n");
-            return -1;
-        }
-    }
-    return 0;
-}
-
 //PAGEBREAK!
 void
 lapicinit(int c)
@@ -151,23 +130,6 @@ microdelay(int us)
 {
 }

-
-// Send IPI
-void
-lapic_ipi(int cpu, int ino)
-{
-  lapicw(ICRHI, cpu << 24);
-  lapicw(ICRLO, FIXED | DEASSERT | ino);
-  if (apic_icr_wait() < 0)
-    panic("lapic_ipi: icr_wait failure");
-}
-
-void
-lapic_tlbflush(uint cpu)
-{
-  lapic_ipi(cpu, T_TLBFLUSH);
-}
-
 #define IO_RTC  0x70

 // Start additional processor running bootstrap code at addr.

--- a/trap.c
+++ b/trap.c
@@ -73,10 +73,6 @@ trap(struct trapframe *tf)
            cpu->id, tf->cs, tf->eip);
    lapiceoi();
    break;
-  case T_TLBFLUSH:
-    lapiceoi();
-    lcr3(rcr3());
-    break;
   
  //PAGEBREAK: 13
  default:

--- a/traps.h
+++ b/traps.h
@@ -25,7 +25,6 @@
 // These are arbitrarily chosen, but with care not to overlap
 // processor defined exceptions or interrupt vectors.
 #define T_SYSCALL       64      // system call
-#define T_TLBFLUSH      65      // flush TLB
 #define T_DEFAULT      500      // catchall

 #define T_IRQ0          32      // IRQ 0 corresponds to int T_IRQ

--- a/vm.c
+++ b/vm.c
@@ -137,11 +137,6 @@ loadvm(struct proc *p)

  lcr3(PADDR(p->pgdir));  // switch to new address space
  popcli();
-
-  // Conservatively flush other processor's TLBs  
-  // XXX lazy--just 2 cpus, but xv6 doesn't need shootdown anyway.
-  if (cpu->id == 0) lapic_tlbflush(1);
-  else lapic_tlbflush(0);
 }

 // Setup kernel part of a page table. Linear adresses map one-to-one