Use the PIT to time the CPU clock, use rdtsc to implement microdelay.

ef3ccaee · Silas Boyd-Wickizer · 5b532e09 · ef3ccaee · ef3ccaee · ef3ccaee
--- a/Makefile
+++ b/Makefile
@@ -23,7 +23,6 @@ ASFLAGS = -m64 -gdwarf-2
 LDFLAGS += -m elf_x86_64

 OBJS = \
-	asm.o \
 	bio.o \
 	cga.o \
 	condvar.o \
@@ -33,6 +32,7 @@ OBJS = \
 	fs.o \
 	ioapic.o \
 	lapic.o \
+	hz.o \
 	kalloc.o \
 	kbd.o \
 	main.o \

--- a/amd64.h
+++ b/amd64.h
@@ -25,12 +25,6 @@ stosb(void *addr, int data, int cnt)
                 "memory", "cc");
 }

-static inline void
-microdelay(u32 delay)
-{
-  
-}
-
 static inline u32
 xchg32(volatile u32 *addr, u32 newval)
 {

--- a/hz.c
+++ b/hz.c
+// Intel 8253/8254/82C54 Programmable Interval Timer (PIT).
+// http://en.wikipedia.org/wiki/Intel_8253
+
+#include "types.h"
+#include "amd64.h"
+
+#define IO_TIMER1       0x040           // 8253 Timer #1
+#define TIMER_FREQ      1193182
+#define	TIMER_CNTR      (IO_TIMER1 + 0)	// timer counter port
+#define TIMER_MODE      (IO_TIMER1 + 3) // timer mode port
+#define TIMER_SEL0      0x00    // select counter 0
+#define TIMER_TCOUNT    0x00    // mode 0, terminal count
+#define TIMER_16BIT     0x30    // r/w counter 16 bits, LSB first
+#define TIMER_STAT      0xe0    // read status mode
+#define TIMER_STAT0     (TIMER_STAT | 0x2)  // status mode counter 0
+
+u64 cpuhz;
+
+void
+microdelay(u64 delay)
+{
+  u64 tscdelay = (cpuhz * delay) / 1000000;
+  u64 s = rdtsc();
+  while (rdtsc() - s < tscdelay)
+    nop_pause();
+}
+
+void
+inithz(void)
+{
+  // Setup PIT for terminal count starting from 2^16 - 1
+  u64 ticks = 0x000000000000FFFFull;
+  outb(TIMER_MODE, TIMER_SEL0 | TIMER_TCOUNT | TIMER_16BIT);  
+  outb(IO_TIMER1, ticks % 256);
+  outb(IO_TIMER1, ticks / 256);
+
+  // Wait until OUT bit of status byte is set
+  u64 s = rdtsc();
+  do {
+    outb(TIMER_MODE, TIMER_STAT0);
+  } while (!(inb(TIMER_CNTR) & 0x80));
+  u64 e = rdtsc();
+
+  cpuhz = ((e-s)*10000000) / ((ticks*10000000)/TIMER_FREQ);
+}
--- a/kernel.h
+++ b/kernel.h
@@ -81,6 +81,9 @@ int             dirlink(struct inode*, char*, u32);
 void            dir_init(struct inode *dp);
 void	        dir_flush(struct inode *dp);

+// hz.c
+void            microdelay(u64);
+
 // ide.c
 void            ideinit(void);
 void            ideintr(void);

--- a/main.c
+++ b/main.c
@@ -22,12 +22,10 @@ extern void initbio(void);
 extern void initinode(void);
 extern void initdisk(void);
 extern void inituser(void);
+extern void inithz(void);

 static volatile int bstate;

-// Common CPU setup code.
-// Bootstrap CPU comes here from mainc().
-// Other CPUs jump here from bootother.S.
 void
 mpboot(void)
 {
@@ -38,7 +36,6 @@ mpboot(void)
  scheduler();     // start running processes
 }

-// Start the non-boot processors.
 static void
 bootothers(void)
 {
@@ -77,10 +74,12 @@ void
 cmain(void)
 {
  extern pml4e_t kpml4[];
+  extern u64 cpuhz;

  initpg();
  initseg();
-  inittls();
+  inittls();       // thread local storage
+  inithz();        // CPU Hz, microdelay
  initpic();       // interrupt controller
  initioapic();
  inituart();
@@ -97,7 +96,7 @@ cmain(void)
  initinode();     // inode cache
  initdisk();      // disk

-  cprintf("ncpu %d\n", ncpu);
+  cprintf("ncpu %d %lu MHz\n", ncpu, cpuhz / 1000000);

  inituser();      // first user process
  bootothers();    // start other processors